[Intel-gfx] [PATCH v4 02/12] drm/i915: Fix 852GM/GMV cdclk
Mika Kahola
mika.kahola at intel.com
Fri May 22 01:22:32 PDT 2015
From: Ville Syrjälä <ville.syrjala at linux.intel.com>
It seems 852GM/GMV uses a different HPLLCC encoding than the other
85x platforms. For 852GM/GMV cdclk is always 133MHz. Try to detect that
using the PCI revision (sinc the device ID seems useless for that). I'm
not at all sure this is a good idea, but according to the specs it
should work.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
v2: Rebased to the latest
v3: Rebased to the latest
Reviewed-by: Mika Kahola <mika.kahola at intel.com>
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 64debfb..4b17aad 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6631,6 +6631,14 @@ static int i85x_get_display_clock_speed(struct drm_device *dev)
{
u16 hpllcc = 0;
+ /*
+ * 852GM/852GMV only supports 133 MHz and the HPLLCC
+ * encoding is different :(
+ * FIXME is this the right way to detect 852GM/852GMV?
+ */
+ if (dev->pdev->revision == 0x1)
+ return 133333;
+
pci_bus_read_config_word(dev->pdev->bus,
PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
--
1.9.1
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