[Intel-gfx] [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Daniel Vetter]

On Tue, May 26, 2015 at 12:57:26PM +0300, Jani Nikula wrote:
> On Tue, 26 May 2015, Daniel Vetter <daniel at ffwll.ch> wrote:
> > On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
> >> BXT supports following intermediate link rates for edp:
> >> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> >> Adding support for programming the intermediate rates.
> >> 
> >> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> >> required rate (Ville)
> >> v3: 'clock' has the selected value, no need to use link_bw or rate_select
> >> for selecting pll(Ville)
> >> v4: Make bxt_dp_clk_val const and remove size (Ville)
> >> v5: Rebased
> >> 
> >> Signed-off-by: Sonika Jindal <sonika.jindal at intel.com>
> >> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> >
> > This time applied for really. Somehow the previous attempt fell short, and
> > digging into git reflog didn't reveal any clues. Sorry for the mess I've
> > made.
> 
> Please drop this, the rebase does not take into account
> 
> commit b6dc71f38a84e36c5445b95f9f7a2dac6b25636f
> Author: Vandana Kannan <vandana.kannan at intel.com>
> Date:   Wed May 13 12:18:52 2015 +0530
> 
>     drm/i915/bxt: Port PLL programming BUN
> 
> and now leaves vco at zero.

Yeah dropped again. I didn't do the rebase myself because of these
functional conflicts, but then totally forgot to check that Sonika
bothered to run the patch first.

Generally when I ask for a rebase it means that there's something
nontrivial going on ...

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch