[Intel-gfx] [v3] drm/i915/skl: While sanitizing cdclock check the SWF18 as well

[Ville Syrjälä]

On Thu, Nov 05, 2015 at 03:05:58PM +0530, Shobhit Kumar wrote:
> SWF18 is set if the display has been intialized by the pre-os. It also
> gives what configuration is enabled on which pipe. In skl_sanitize_cdclk,
> the DPLL sanity check can pass even if GOP/VBIOS is not loaded as BIOS
> enables DPLL for integrated audio codec related programming.
> So fisrt check if SWF18 is set and then follow through with other DPLL
> and CDCLK verification. If not set then for sure we need to sanitize the
> cdclock.
> 
> v2: Update the commit message for clarity (Siva)
> v3: Correct the mask to check for bits[23:0] instead of only bits[16:0].
>     Had missed checking for PIPE C altogether. Remaining are reserved (Siva)
> 
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 3 +++
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9ee9481..bd476ff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5006,6 +5006,9 @@ enum skl_disp_power_wells {
>  #define SWF1(i)	(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
>  #define SWF3(i)	(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
>  
> +/* VBIOS flag for display initialized status */
> +#define GEN6_SWF18  (dev_priv->info.display_mmio_offset + 0x4F060)

Could you steal the ILK_SWF() register define from my patch at?
http://lists.freedesktop.org/archives/intel-gfx/2015-November/079480.html
Would avoid a bit of churn at least.

Otherwise this seems reasonable enough to me.

> +
>  /* Pipe B */
>  #define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
>  #define _PIPEBCONF		(dev_priv->info.display_mmio_offset + 0x71008)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 103cacb..81668b0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5761,6 +5761,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	uint32_t cdctl = I915_READ(CDCLK_CTL);
>  	int freq = dev_priv->skl_boot_cdclk;
>  
> +	/*
> +	 * check if the pre-os intialized the display
> +	 * There is SWF18 scratchpad register defined which is set by the
> +	 * pre-os which can be used by the OS drivers to check the status
> +	 */
> +	if ((I915_READ(GEN6_SWF18) & 0x00FFFFFF) == 0)
> +		goto sanitize;
> +
>  	/* Is PLL enabled and locked ? */
>  	if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
>  		goto sanitize;
> -- 
> 2.4.3

-- 
Ville Syrjälä
Intel OTC