[Intel-gfx] [PATCH 03/31] drm/i915: Add IPS DockBook.

[Rodrigo Vivi]

Intermediate Pixel Storage documentation.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
---
 Documentation/DocBook/gpu.tmpl   |  5 +++++
 drivers/gpu/drm/i915/intel_ips.c | 37 ++++++++++++++++++++++++++++++++++---
 2 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
index 54dfd28..e2e01cd 100644
--- a/Documentation/DocBook/gpu.tmpl
+++ b/Documentation/DocBook/gpu.tmpl
@@ -4002,6 +4002,11 @@ int num_ioctls;</synopsis>
 !Idrivers/gpu/drm/i915/intel_fbc.c
       </sect2>
       <sect2>
+	<title>Intermediate Pixel Storage (IPS)</title>
+!Pdrivers/gpu/drm/i915/intel_ips.c Intermediate Pixel Storage (IPS)
+!Idrivers/gpu/drm/i915/intel_ips.c
+      </sect2>
+      <sect2>
         <title>Display Refresh Rate Switching (DRRS)</title>
 !Pdrivers/gpu/drm/i915/intel_dp.c Display Refresh Rate Switching (DRRS)
 !Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_set_drrs_state
diff --git a/drivers/gpu/drm/i915/intel_ips.c b/drivers/gpu/drm/i915/intel_ips.c
index 5c659a3..573bc31 100644
--- a/drivers/gpu/drm/i915/intel_ips.c
+++ b/drivers/gpu/drm/i915/intel_ips.c
@@ -21,12 +21,21 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-/* IPS only exists on ULT machines and is tied to pipe A. */
-
 #include "intel_drv.h"
 #include "i915_drv.h"
 
-
+/**
+ * DOC: Intermediate Pixel Storage (IPS)
+ *
+ * Haswell-ULT and Broadwell have support to IPS feature where pixel information
+ * can be stored in a special buffer in display that can allow memory to get
+ * into deeper power states and spend more time in low power states
+ *
+ * IPS is only supported on Pipe A with pipe pixel format 8:8:8 or less
+ * and when pixel rate is lesser than 95% of the CDCLK frequency.
+ *
+ * IPS cannot be enabled on the pipe when there is no plane enabled.
+ */
 static void assert_plane(struct drm_i915_private *dev_priv,
 			 enum plane plane, bool state)
 {
@@ -70,6 +79,14 @@ static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
 	       dev_priv->max_cdclk_freq * 95 / 100;
 }
 
+/**
+ * intel_ips_ready - Is IPS Ready?
+ * @crtc: intel crtc
+ * @pipe_config: Pipe config
+ *
+ * This function is called to know if IPS is ready to be enabled
+ * on this pipe.
+ */
 bool intel_ips_ready(struct intel_crtc *crtc,
 		     struct intel_crtc_state *pipe_config)
 {
@@ -81,6 +98,13 @@ bool intel_ips_ready(struct intel_crtc *crtc,
 	       pipe_config_supports_ips(dev_priv, pipe_config);
 }
 
+/**
+ * intel_ips_enable - Enable IPS
+ * @crtc: intel crtc
+ *
+ * This function is called to enable IPS on certain pipe.
+ * All needed conditions should've checked already by intel_ips_ready.
+ */
 void intel_ips_enable(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
@@ -121,6 +145,13 @@ void intel_ips_enable(struct intel_crtc *crtc)
 	}
 }
 
+/**
+ * intel_ips_disable - Disable IPS
+ * @crtc: intel crtc
+ *
+ * This function is called to disable IPS on certain pipe whenever it is needed
+ * to disable IPS on the pipe.
+ */
 void intel_ips_disable(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
-- 
2.4.3