[Intel-gfx] [RFC 0/5] LRC irq handler cleanups

[Tvrtko Ursulin]

On 10/11/15 11:36, Chris Wilson wrote:
> On Tue, Nov 10, 2015 at 10:59:40AM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>>
>> Some random bits to make the LRC irq handler do fewer branching,
>> locking and VMA lookups per interrupt handled.
>>
>> I failed to measure a significant gain on a powerful chip but it
>> definitely results in fewer instructions and branches in the hot
>> path. So maybe it would help a lower power chip more.
>>
>> Possibly makes the first run of gem_exec_nop have less variance
>> eg. branch predictor maybe gets warmed up sooner but I am not
>> completely confident in this interpretation.
>
> I have previously posted these and so much more.

Thread subject ?

Regards,

Tvrtko