[Intel-gfx] [PATCH] drm/i915: Reset dpll_hw_state when selecting a new pll on hsw

[Jani Nikula]

On Wed, 11 Nov 2015, Ander Conselvan De Oliveira <conselvan2 at gmail.com> wrote:
> On Tue, 2015-11-10 at 14:53 +0200, Jani Nikula wrote:
>> Ander, Maarten, where are we with this? Is it horribly wrong to merge
>> the original patch in this ever-growing and diverging thread?
>
> I think the patch as is will cause problems with DP, since we might clear the
> pll selection made in hsw_dp_set_ddi_pll_sel(). I think the easy fix
> disregarding the discussion in this thread is to drop another memset in
>  intel_crt_compute_config(). Like this


Ander, please post this as a proper patch for review.

BR,
Jani.

>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index b84aaa0..ad099f3 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -278,6 +278,9 @@ static bool intel_crt_compute_config(struct intel_encoder
> *encoder,
>  
>         /* FDI must always be 2.7 GHz */
>         if (HAS_DDI(dev)) {
> +               memset(&pipe_config->dpll_hw_state, 0,
> +                      sizeof(pipe_config->dpll_hw_state));
> +
>                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
>                 pipe_config->port_clock = 135000 * 2;
>         }
>
> Ander

-- 
Jani Nikula, Intel Open Source Technology Center