[Intel-gfx] [PATCH libdrm] intel/kbl: Add Kabylake PCI IDs

[Rodrigo Vivi]

Also, following kernel definition Kabylake is Skylake.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
---
 intel/intel_chipset.h | 51 ++++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 48 insertions(+), 3 deletions(-)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 253ea71..b9bd091 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -181,6 +181,25 @@
 #define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A
 #define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
 
+#define PCI_CHIP_KABYLAKE_ULT_GT2      0x5916
+#define PCI_CHIP_KABYLAKE_ULT_GT1_5    0x5913
+#define PCI_CHIP_KABYLAKE_ULT_GT1      0x5906
+#define PCI_CHIP_KABYLAKE_ULT_GT3      0x5926
+#define PCI_CHIP_KABYLAKE_ULT_GT2F     0x5921
+#define PCI_CHIP_KABYLAKE_ULX_GT1_5    0x5915
+#define PCI_CHIP_KABYLAKE_ULX_GT1      0x590E
+#define PCI_CHIP_KABYLAKE_ULX_GT2      0x591E
+#define PCI_CHIP_KABYLAKE_DT_GT2       0x5912
+#define PCI_CHIP_KABYLAKE_DT_GT1_5     0x5917
+#define PCI_CHIP_KABYLAKE_DT_GT1       0x5902
+#define PCI_CHIP_KABYLAKE_HALO_GT2     0x591B
+#define PCI_CHIP_KABYLAKE_HALO_GT3     0x592B
+#define PCI_CHIP_KABYLAKE_HALO_GT1     0x590B
+#define PCI_CHIP_KABYLAKE_SRV_GT2      0x591A
+#define PCI_CHIP_KABYLAKE_SRV_GT3      0x592A
+#define PCI_CHIP_KABYLAKE_SRV_GT1      0x590A
+#define PCI_CHIP_KABYLAKE_WKS_GT2      0x591D
+
 #define PCI_CHIP_BROXTON_0		0x0A84
 #define PCI_CHIP_BROXTON_1		0x1A84
 #define PCI_CHIP_BROXTON_2		0x5A84
@@ -362,9 +381,35 @@
 				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3	|| \
 				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
 
-#define IS_SKYLAKE(devid)	(IS_SKL_GT1(devid) || \
-				 IS_SKL_GT2(devid) || \
-				 IS_SKL_GT3(devid))
+#define IS_KBL_GT1(devid)       ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_ULT_GT1|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_DT_GT1||  \
+                                 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_SRV_GT1)
+
+#define IS_KBL_GT2(devid)       ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_DT_GT2||  \
+                                 (devid) == PCI_CHIP_KABYLAKE_HALO_GT2|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_SRV_GT2|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
+
+#define IS_KBL_GT3(devid)       ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_HALO_GT3|| \
+                                 (devid) == PCI_CHIP_KABYLAKE_SRV_GT3)
+
+#define IS_KABYLAKE(devid)      (IS_KBL_GT1(devid) || \
+                                 IS_KBL_GT2(devid) || \
+                                 IS_KBL_GT3(devid))
+
+#define IS_SKYLAKE(devid)       (IS_KABYLAKE(devid) || \
+                                 IS_SKL_GT1(devid) || \
+                                 IS_SKL_GT2(devid) || \
+                                 IS_SKL_GT3(devid))
 
 #define IS_BROXTON(devid)	((devid) == PCI_CHIP_BROXTON_0	|| \
 				 (devid) == PCI_CHIP_BROXTON_1	|| \
-- 
2.4.3