[Intel-gfx] [PATCH] drm/i915: Allow userptr backchannel for passing around GTT mappings

Chris Wilson chris at chris-wilson.co.uk
Tue Oct 6 05:24:38 PDT 2015

On Tue, Oct 06, 2015 at 02:12:31PM +0200, Daniel Vetter wrote:
> On Thu, Oct 01, 2015 at 12:36:05PM +0100, Chris Wilson wrote:
> > Once userptr becomes part of client API, it is almost a certainty that
> > eventually someone will try to create a new object from a mapping of
> > another client object, e.g.
> > 
> > new = vaImport(vaMap(old, &size), size);
> > 
> > (using a hypothethical API, not meaning to pick on anyone!)
> > 
> > Since this is actually fairly safe to implement and to allow for a GTT
> > mapping (since it is within a single process space and the memory access
> > passes the standard permissions test) let us not limit the Client
> > possibilities.
> > 
> > v2: sfelling pixes
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: Gwenole Beauchesne <gwenole.beauchesne at intel.com>
> > Cc: MichaƂ Winiarski <michal.winiarski at intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> This feels like a really big can of worms, since all the apis I've seen
> thus far have been rather explicit that you can only import malloc'ed
> memory.

Weirdly no one even brought it up as an issue for AMD_pinned_memory.
Nothing in the spec says you can't
		     glMapBuffer(GL_PIXEL_UNPACK_BUFFER, ...));

Not that I would expect it to always work.

> Also tiling and stuff like this ...

Indeed, it is the only way to get tiling right... The only question is
whether every userptr mapping should be a unique bo (this also has the
effect of return a new handle for an existing userptr mapping to the
same exact address range). Note that the memory address is still
controlled by the earlier bo, so it will always remain linear, and with
the second handle the user still has to object all the normal userptr

As you probably guess Gwenole raise the question of whether this
behaviour would be possible to implement.

Chris Wilson, Intel Open Source Technology Centre

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