[Intel-gfx] [PATCH 12/12] drm/i915/ivb: Simplify row chicken setup logic

[Mika Kuoppala]

We always write the ROW_CHICKEN2. Make this more clear
by writing it unconditionally.

Signed-off-by: Mika Kuoppala <mika.kuoppala at intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8bc1d3b..ec77e04 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6685,16 +6685,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	WA_WRITE(MMIO, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
 	WA_WRITE(MMIO, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
 
-	if (IS_IVB_GT1(dev))
-		WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2,
-				  DOP_CLOCK_GATING_DISABLE);
-	else {
-		/* must write both registers */
-		WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2,
-				  DOP_CLOCK_GATING_DISABLE);
+	WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2,
+			  DOP_CLOCK_GATING_DISABLE);
+
+	/* must write both registers */
+	if (!IS_IVB_GT1(dev))
 		WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2_GT2,
 				  DOP_CLOCK_GATING_DISABLE);
-	}
 
 	/* WaForceL3Serialization:ivb */
 	WA_CLR_BIT(MMIO, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
-- 
2.1.4