[Intel-gfx] [PATCH 10/12] drm/i915/hsw: Use mmio workarounds in init clock gating

[Mika Kuoppala]

For workarounds written in haswells's init clock gating path,
use mmio workaround list.

Signed-off-by: Mika Kuoppala <mika.kuoppala at intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 35 +++++++++++++++--------------------
 1 file changed, 15 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7e01ef7..b2626c2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6608,29 +6608,26 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 	ilk_init_lp_watermarks(dev);
 
 	/* L3 caching of data atomics doesn't work -- disable it. */
-	I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
-	I915_WRITE(HSW_ROW_CHICKEN3,
-		   _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
+	WA_WRITE(MMIO, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
+	WA_SET_BIT_MASKED(MMIO, HSW_ROW_CHICKEN3,
+			  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE);
 
 	/* This is required by WaCatErrorRejectionIssue:hsw */
-	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
-			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
-			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
+	WA_SET_BIT(MMIO, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
 	/* WaVSRefCountFullforceMissDisable:hsw */
-	I915_WRITE(GEN7_FF_THREAD_MODE,
-		   I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
+	WA_CLR_BIT(MMIO, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
 
 	/* WaDisable_RenderCache_OperationalFlush:hsw */
-	I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
+	WA_CLR_BIT_MASKED(MMIO, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
 
 	/* enable HiZ Raw Stall Optimization */
-	I915_WRITE(CACHE_MODE_0_GEN7,
-		   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+	WA_CLR_BIT_MASKED(MMIO, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 
 	/* WaDisable4x2SubspanOptimization:hsw */
-	I915_WRITE(CACHE_MODE_1,
-		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
+	WA_SET_BIT_MASKED(MMIO, CACHE_MODE_1,
+			  PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
 
 	/*
 	 * BSpec recommends 8x4 when MSAA is used,
@@ -6640,19 +6637,17 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 	 * disable bit, which we don't touch here, but it's good
 	 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 	 */
-	I915_WRITE(GEN7_GT_MODE,
-		   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
+	WA_SET_FIELD_MASKED(MMIO, GEN7_GT_MODE,
+			    GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4);
 
 	/* WaSampleCChickenBitEnable:hsw */
-	I915_WRITE(HALF_SLICE_CHICKEN3,
-		   _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
+	WA_SET_BIT_MASKED(MMIO, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
 
 	/* WaSwitchSolVfFArbitrationPriority:hsw */
-	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
+	WA_SET_BIT(MMIO, GAM_ECOCHK, HSW_ECOCHK_ARB_PRIO_SOL);
 
 	/* WaRsPkgCStateDisplayPMReq:hsw */
-	I915_WRITE(CHICKEN_PAR1_1,
-		   I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
+	WA_SET_BIT(MMIO, CHICKEN_PAR1_1, FORCE_ARB_IDLE_PLANES);
 
 	lpt_init_clock_gating(dev);
 }
-- 
2.1.4