[Intel-gfx] [PATCH 5/6] drm/i915/hsw: Move L3 atomics workaround to the workaround list.

[Francisco Jerez]

This makes sure that the workaround is not accidentally undone by some
process (which is possible because the HSW_SCRATCH1 and
HSW_ROW_CHICKEN3 registers are partially whitelisted), what could
cause the next context to be created to hang if it wasn't expecting L3
atomics to be enabled.

Signed-off-by: Francisco Jerez <currojerez at riseup.net>
---
 drivers/gpu/drm/i915/intel_pm.c         |  5 -----
 drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++++++++++++
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 60d120c..d495043 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6585,11 +6585,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 
 	ilk_init_lp_watermarks(dev);
 
-	/* L3 caching of data atomics doesn't work -- disable it. */
-	I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
-	I915_WRITE(HSW_ROW_CHICKEN3,
-		   _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
-
 	/* This is required by WaCatErrorRejectionIssue:hsw */
 	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
 			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c4c39c4..4cb9f5c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -902,6 +902,18 @@ static int vlv_init_workarounds(struct intel_engine_cs *ring)
 
 static int hsw_init_workarounds(struct intel_engine_cs *ring)
 {
+	struct drm_i915_private *dev_priv = ring->dev->dev_private;
+
+	/*
+	 * L3 caching of data atomics can easily cause a full-system
+	 * hang if not used with extreme care -- Disable it on all
+	 * contexts by default, userspace is free to re-enable them if
+	 * it knows what it's doing.
+	 */
+	WA_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
+	WA_WRITE(HSW_ROW_CHICKEN3,
+		 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
+
 	/*
 	 * Set up the default L3 partitioning of the hardware of 32
 	 * ways (i.e. 256 KB on GT2 parts) for the URB and another 32
-- 
2.5.1