[Intel-gfx] [PATCH 3/3] drm/i915/chv: remove pre-production hardware workarounds

[Daniel Vetter]

On Wed, Oct 07, 2015 at 04:28:48PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 07, 2015 at 11:17:46AM +0300, Jani Nikula wrote:
> > Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 55 +++++++++++++++++------------------------
> >  1 file changed, 22 insertions(+), 33 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 60d120c472ab..598ee4c8d86e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5061,32 +5061,27 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
> >  	struct drm_device *dev = dev_priv->dev;
> >  	u32 val, rp0;
> >  
> > -	if (dev->pdev->revision >= 0x20) {
> 
> Yep. C0 is the first production stepping.
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Applied both patch 1&3 from this series, with gcc appeased on this patch
here.

Thanks, Daniel
> 
> > -		val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> > +	val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> >  
> > -		switch (INTEL_INFO(dev)->eu_total) {
> > -		case 8:
> > -				/* (2 * 4) config */
> > -				rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
> > -				break;
> > -		case 12:
> > -				/* (2 * 6) config */
> > -				rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
> > -				break;
> > -		case 16:
> > -				/* (2 * 8) config */
> > -		default:
> > -				/* Setting (2 * 8) Min RP0 for any other combination */
> > -				rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
> > -				break;
> > -		}
> > -		rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
> > -	} else {
> > -		/* For pre-production hardware */
> > -		val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> > -		rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
> > -		       PUNIT_GPU_STATUS_MAX_FREQ_MASK;
> > +	switch (INTEL_INFO(dev)->eu_total) {
> > +	case 8:
> > +		/* (2 * 4) config */
> > +		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
> > +		break;
> > +	case 12:
> > +		/* (2 * 6) config */
> > +		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
> > +		break;
> > +	case 16:
> > +		/* (2 * 8) config */
> > +	default:
> > +		/* Setting (2 * 8) Min RP0 for any other combination */
> > +		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
> > +		break;
> >  	}
> > +
> > +	rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
> > +
> >  	return rp0;
> >  }
> >  
> > @@ -5105,15 +5100,9 @@ static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
> >  	struct drm_device *dev = dev_priv->dev;
> >  	u32 val, rp1;
> >  
> > -	if (dev->pdev->revision >= 0x20) {
> > -		val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> > -		rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
> > -	} else {
> > -		/* For pre-production hardware */
> > -		val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> > -		rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
> > -		       PUNIT_GPU_STATUS_MAX_FREQ_MASK);
> > -	}
> > +	val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
> > +	rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
> > +
> >  	return rp1;
> >  }
> >  
> > -- 
> > 2.1.4
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch