[Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4

ville.syrjala at linux.intel.com ville.syrjala at linux.intel.com
Wed Oct 7 12:08:24 PDT 2015

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

We accidentally lost the initial DPLL register write in
1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M

The "three times for luck" hack probably saved us from a total
disaster. But anyway, bring the initial write back so that the
code actually makes some sense.

Cc: stable at vger.kernel.org
Cc: Nick Bowler <nbowler at draconx.ca>
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 147e700..f4fdff9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
 			   I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
+	I915_WRITE(reg, dpll);
 	/* Wait for the clocks to stabilize. */

More information about the Intel-gfx mailing list