[Intel-gfx] [PATCH 27/43] drm/i915: Fix a few bad hex numbers in register defines

[Jesse Barnes]

On 09/18/2015 10:03 AM, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> A few register mask defines were missing the '0x' from hex numbers. Or
> at least I assume those were meant to be hex numbers. Put the '0x' in
> place.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 21d49e7..02f0935 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4234,7 +4234,7 @@ enum skl_disp_power_wells {
>  #define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL	(1 << 14)
>  #define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL	(1 << 13)
>  #define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL	(1 << 12)
> -#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5)
> +#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
>  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
>  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
>  
> @@ -7819,7 +7819,7 @@ enum skl_disp_power_wells {
>  #define  VIRTUAL_CHANNEL_SHIFT				6
>  #define  VIRTUAL_CHANNEL_MASK				(3 << 6)
>  #define  DATA_TYPE_SHIFT				0
> -#define  DATA_TYPE_MASK					(3f << 0)
> +#define  DATA_TYPE_MASK					(0x3f << 0)
>  /* data type values, see include/video/mipi_display.h */
>  
>  #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
> 

Hah!  Maybe they're supposed to be floats though!  We should use more
floats in masks in general I believe.

Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>