[Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes

[Daniel Vetter]

On Tue, Oct 13, 2015 at 03:45:58PM +0300, Jani Nikula wrote:
> On Wed, 26 Aug 2015, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> > On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote:
> >> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> >> > In order to flush the results from in-batch pipecontrol writes (used for
> >> > example in glQuery) before declaring the batch complete (and so declaring
> >> > the query results coherent), we need to set the FlushEnable bit in our
> >> > flushing pipecontrol. The FlushEnable bit "waits until all previous
> >> > writes of immediate data from post-sync circles are complete before
> >> > executing the next command".
> >> > 
> >> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> >> > Cc: stable at vger.kernel.org
> >> 
> >> Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
> >> bugzilla or why is this cc: stable?
> >
> > I get GPU hangs on byt without flushing these writes (running ue4).
> > piglit has examples where the flush is required for correct rendering.
> 
> Daniel, does this satisfy your question? We've had an r-b from Ville for
> a long time.

Yeah, just add that bit to the commit message to justify cc: stable.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch