[Intel-gfx] [PATCH] drm/i915/skl+: Enable gamma and CSC on bottom color.

[Bob Paauwe]

To stay consisent with how we're programming all the other planes,
enable gamma and CSC on the bottom color.  Without this, we fail the
the kms_universal_plane functional tests because the black primary plane
is brighter (gamma corrected) than the disabled plane case.  If the bottom
color is also gamma/csc corrected, then the disiabled case will match the
black plane case.

testcase: igt/kms_universal_plane/universal-plane-pipe-[ABC]-functional
CC: Konduru, Chandra <chandra.konduru at intel.com>
cc: Kevin Strasser <kevin.strasser at linux.intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 10 ++++++++++
 drivers/gpu/drm/i915/intel_display.c |  7 +++++++
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 724f057..9ad330b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4479,6 +4479,16 @@ enum skl_disp_power_wells {
 #define   PIPEMISC_DITHER_TYPE_SP	(0<<2)
 #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
 
+#define _PIPE_BOTTOM_COLOR_A           0x70034
+#define _PIPE_BOTTOM_COLOR_B           0x71034
+#define _PIPE_BOTTOM_COLOR_C           0x72034
+#define   PIPE_BOTTOM_GAMMA_ENABLE     (1<<31)
+#define   PIPE_BOTTOM_CSC_ENABLE       (1<<30)
+#define   PIPE_BOTTOM_COLOR_MASK       0x3FFFFFFF
+#define PIPE_BOTTOM_COLOR(pipe) _PIPE3(pipe, _PIPE_BOTTOM_COLOR_A, \
+                                      _PIPE_BOTTOM_COLOR_B, \
+                                      _PIPE_BOTTOM_COLOR_C)
+
 #define VLV_DPFLIPSTAT				(VLV_DISPLAY_BASE + 0x70028)
 #define   PIPEB_LINE_COMPARE_INT_EN		(1<<29)
 #define   PIPEB_HLINE_INT_EN			(1<<28)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3b4bacf..7665730 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4949,6 +4949,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	struct intel_crtc_state *pipe_config =
 		to_intel_crtc_state(crtc->state);
 	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
+	u32 bottom;
 
 	if (WARN_ON(intel_crtc->active))
 		return;
@@ -5033,6 +5034,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 		intel_wait_for_vblank(dev, hsw_workaround_pipe);
 		intel_wait_for_vblank(dev, hsw_workaround_pipe);
 	}
+
+	if (INTEL_INFO(dev)->gen >= 9) {
+		bottom = I915_READ(PIPE_BOTTOM_COLOR(pipe));
+		bottom |= (PIPE_BOTTOM_CSC_ENABLE | PIPE_BOTTOM_GAMMA_ENABLE);
+		I915_WRITE(PIPE_BOTTOM_COLOR(pipe), bottom);
+	}
 }
 
 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
-- 
2.4.3