[Intel-gfx] [PATCH RESEND] drm/i915: disable CPU PWM also on LPT/SPT backlight disable

[Ville Syrjälä]

On Wed, Oct 28, 2015 at 01:57:09PM +0200, Jani Nikula wrote:
> Although we don't support or enable CPU PWM with LPT/SPT based systems,
> it may have been enabled prior to loading the driver. Disable the CPU
> PWM on LPT/SPT backlight disable to avoid warnings on LCPLL disable.
> 
> The issue has been present on BDW since BDW enabling, but was recently
> introduced on HSW with
> 
> commit 437b15b8017e0d946453c10794b0c5d4591cf180
> Author: Jani Nikula <jani.nikula at intel.com>
> Date:   Fri Sep 4 16:55:13 2015 +0300
> 
>     drm/i915: use pch backlight override on hsw too
> 
> Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Reference: http://mid.gmane.org/87y4frhwsn.fsf@yhuang-dev.intel.com
> Reported-by: kernel test robot <ying.huang at intel.com>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>

Not seeing the warning anymore during
./scripts/run-tests.sh -t basic -x reload -x suspend
on my HSW-ULT

Tested-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_panel.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index b05c6d9b3be7..a24df35e11e7 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -732,6 +732,20 @@ static void lpt_disable_backlight(struct intel_connector *connector)
>  
>  	intel_panel_actually_set_backlight(connector, 0);
>  
> +	/*
> +	 * Although we don't support or enable CPU PWM with LPT/SPT based
> +	 * systems, it may have been enabled prior to loading the
> +	 * driver. Disable to avoid warnings on LCPLL disable.
> +	 *
> +	 * This needs rework if we need to add support for CPU PWM on PCH split
> +	 * platforms.
> +	 */
> +	tmp = I915_READ(BLC_PWM_CPU_CTL2);
> +	if (tmp & BLM_PWM_ENABLE) {
> +		DRM_DEBUG_KMS("cpu backlight was enabled, disabling\n");
> +		I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
> +	}
> +
>  	tmp = I915_READ(BLC_PWM_PCH_CTL1);
>  	I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
>  }
> -- 
> 2.1.4

-- 
Ville Syrjälä
Intel OTC