[Intel-gfx] [PATCH v2] drm/i915: remove an extra level of indirection in PCI ID list
Rodrigo Vivi
rodrigo.vivi at gmail.com
Wed Oct 28 12:38:01 PDT 2015
On Wed, Oct 28, 2015 at 12:32 PM, Jani Nikula <jani.nikula at intel.com> wrote:
> On Wed, 28 Oct 2015, Rodrigo Vivi <rodrigo.vivi at gmail.com> wrote:
>> I like this idea, but a small complain is that we had already 2
>> reviewed patches at the mailing list waiting to get merged that
>> conflicted with this one.
>
> I was aware of the conflict but failed to see they were reviewed already
> and thought you needed to respin anyway. Sorry for the extra trouble
> caused.
oh, nevermind... you were right...
those depends on the first patch with platform definition that is not
reviewed yet...
please forgive me and ignore my complain ;)
>
> BR,
> Jani.
>
>>
>> Please, next time consider merging the already reviewed patches that
>> touches same part before merging so quickly a patch like this.
>>
>> On Wed, Oct 28, 2015 at 10:52 AM, Jani Nikula <jani.nikula at intel.com> wrote:
>>> On Wed, 28 Oct 2015, Jani Nikula <jani.nikula at intel.com> wrote:
>>>> Add the PCI IDs directly in the pciidlist array instead of defining an
>>>> extra macro. The minor benefit from this is neater diffs when adding to
>>>> the end of the list.
>>>>
>>>> v2: drop the "aka" comment (Ville)
>>>>
>>>> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
>>>> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
>>>
>>> and pushed, thanks for the review.
>>>
>>> BR,
>>> Jani.
>>>
>>>> ---
>>>> drivers/gpu/drm/i915/i915_drv.c | 73 ++++++++++++++++++++---------------------
>>>> 1 file changed, 35 insertions(+), 38 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>>>> index b1f1dec05274..121c5394fa51 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.c
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>>>> @@ -400,44 +400,41 @@ static const struct intel_device_info intel_broxton_info = {
>>>> * and subvendor IDs, we need it to come before the more general IVB
>>>> * PCI ID matches, otherwise we'll use the wrong info struct above.
>>>> */
>>>> -#define INTEL_PCI_IDS \
>>>> - INTEL_I830_IDS(&intel_i830_info), \
>>>> - INTEL_I845G_IDS(&intel_845g_info), \
>>>> - INTEL_I85X_IDS(&intel_i85x_info), \
>>>> - INTEL_I865G_IDS(&intel_i865g_info), \
>>>> - INTEL_I915G_IDS(&intel_i915g_info), \
>>>> - INTEL_I915GM_IDS(&intel_i915gm_info), \
>>>> - INTEL_I945G_IDS(&intel_i945g_info), \
>>>> - INTEL_I945GM_IDS(&intel_i945gm_info), \
>>>> - INTEL_I965G_IDS(&intel_i965g_info), \
>>>> - INTEL_G33_IDS(&intel_g33_info), \
>>>> - INTEL_I965GM_IDS(&intel_i965gm_info), \
>>>> - INTEL_GM45_IDS(&intel_gm45_info), \
>>>> - INTEL_G45_IDS(&intel_g45_info), \
>>>> - INTEL_PINEVIEW_IDS(&intel_pineview_info), \
>>>> - INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
>>>> - INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
>>>> - INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
>>>> - INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
>>>> - INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
>>>> - INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
>>>> - INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
>>>> - INTEL_HSW_D_IDS(&intel_haswell_d_info), \
>>>> - INTEL_HSW_M_IDS(&intel_haswell_m_info), \
>>>> - INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
>>>> - INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
>>>> - INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
>>>> - INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
>>>> - INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
>>>> - INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
>>>> - INTEL_CHV_IDS(&intel_cherryview_info), \
>>>> - INTEL_SKL_GT1_IDS(&intel_skylake_info), \
>>>> - INTEL_SKL_GT2_IDS(&intel_skylake_info), \
>>>> - INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \
>>>> - INTEL_BXT_IDS(&intel_broxton_info)
>>>> -
>>>> -static const struct pci_device_id pciidlist[] = { /* aka */
>>>> - INTEL_PCI_IDS,
>>>> +static const struct pci_device_id pciidlist[] = {
>>>> + INTEL_I830_IDS(&intel_i830_info),
>>>> + INTEL_I845G_IDS(&intel_845g_info),
>>>> + INTEL_I85X_IDS(&intel_i85x_info),
>>>> + INTEL_I865G_IDS(&intel_i865g_info),
>>>> + INTEL_I915G_IDS(&intel_i915g_info),
>>>> + INTEL_I915GM_IDS(&intel_i915gm_info),
>>>> + INTEL_I945G_IDS(&intel_i945g_info),
>>>> + INTEL_I945GM_IDS(&intel_i945gm_info),
>>>> + INTEL_I965G_IDS(&intel_i965g_info),
>>>> + INTEL_G33_IDS(&intel_g33_info),
>>>> + INTEL_I965GM_IDS(&intel_i965gm_info),
>>>> + INTEL_GM45_IDS(&intel_gm45_info),
>>>> + INTEL_G45_IDS(&intel_g45_info),
>>>> + INTEL_PINEVIEW_IDS(&intel_pineview_info),
>>>> + INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
>>>> + INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
>>>> + INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
>>>> + INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
>>>> + INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
>>>> + INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
>>>> + INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
>>>> + INTEL_HSW_D_IDS(&intel_haswell_d_info),
>>>> + INTEL_HSW_M_IDS(&intel_haswell_m_info),
>>>> + INTEL_VLV_M_IDS(&intel_valleyview_m_info),
>>>> + INTEL_VLV_D_IDS(&intel_valleyview_d_info),
>>>> + INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
>>>> + INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
>>>> + INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
>>>> + INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
>>>> + INTEL_CHV_IDS(&intel_cherryview_info),
>>>> + INTEL_SKL_GT1_IDS(&intel_skylake_info),
>>>> + INTEL_SKL_GT2_IDS(&intel_skylake_info),
>>>> + INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
>>>> + INTEL_BXT_IDS(&intel_broxton_info),
>>>> {0, 0, 0}
>>>> };
>>>>
>>>> --
>>>> 2.1.4
>>>>
>>>
>>> --
>>> Jani Nikula, Intel Open Source Technology Center
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx at lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>> --
>> Rodrigo Vivi
>> Blog: http://blog.vivi.eng.br
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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