[Intel-gfx] [PATCH 3/7] drm/i915/skl: Print the DMC firmware status in debugfs

Imre Deak imre.deak at intel.com
Thu Oct 29 08:50:44 PDT 2015


On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote:
> From: Damien Lespiau <damien.lespiau at intel.com>
> 
> Create a new debufs file for it, we'll have a few more things to add
> there.
> 
> v2: Fix checkpatch warning about static const array
> v3: use named initializers (Ville)
> v4: strip out csr_state as it will be removed in future (Ville, Imre)
> 
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com> (v1)
> Signed-off-by: Mika Kuoppala <mika.kuoppala at intel.com>

Reviewed-by: Imre Deak <imre.deak at intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 89ba549..2f53cb1 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2783,6 +2783,32 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
>  	return 0;
>  }
>  
> +static int i915_dmc_info(struct seq_file *m, void *unused)
> +{
> +	struct drm_info_node *node = m->private;
> +	struct drm_device *dev = node->minor->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_csr *csr;
> +
> +	if (!HAS_CSR(dev)) {
> +		seq_puts(m, "not supported\n");
> +		return 0;
> +	}
> +
> +	csr = &dev_priv->csr;
> +
> +	seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
> +	seq_printf(m, "path: %s\n", csr->fw_path);
> +
> +	if (!csr->dmc_payload)
> +		return 0;
> +
> +	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> +		   CSR_VERSION_MINOR(csr->version));
> +
> +	return 0;
> +}
> +
>  static void intel_seq_print_mode(struct seq_file *m, int tabs,
>  				 struct drm_display_mode *mode)
>  {
> @@ -5242,6 +5268,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
>  	{"i915_energy_uJ", i915_energy_uJ, 0},
>  	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
>  	{"i915_power_domain_info", i915_power_domain_info, 0},
> +	{"i915_dmc_info", i915_dmc_info, 0},
>  	{"i915_display_info", i915_display_info, 0},
>  	{"i915_semaphore_status", i915_semaphore_status, 0},
>  	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},




More information about the Intel-gfx mailing list