[Intel-gfx] [PATCH 03/14] drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB

[Paulo Zanoni]

2015-10-29 17:25 GMT-02:00  <ville.syrjala at linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> We get spurious PCH FIFO underruns if we enable the reporting too soon
> after enabling the crtc. Move it to be the last step, after the encoder
> enable. Additionally we need an extra vblank wait, otherwise we still
> get the underruns. Presumably the pipe/fdi isn't yet fully up and running
> otherwise.
>
> For symmetry, disable the PCH underrun reporting as the first thing,
> just before encoder disable, when shutting down the crtc.

Is there any place that describes where/when a FIFO underrun is
expected and where/when one is an actual problem that needs to be
solved? How do we know the underruns avoided by these patch are not a
signal of real bugs?

The fact that we don't get these 100% of the time suggests that maybe
they're avoidable somehow.

Perhaps you could update the commit message with the info.

>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 13 +++++++++----
>  1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 99fb33f..d5cb899 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4874,7 +4874,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>         intel_crtc->active = true;
>
>         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -       intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
>
>         for_each_encoder_on_crtc(dev, crtc, encoder)
>                 if (encoder->pre_enable)
> @@ -4912,6 +4911,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>
>         if (HAS_PCH_CPT(dev))
>                 cpt_verify_modeset(dev, intel_crtc->pipe);
> +
> +       if (intel_crtc->config->has_pch_encoder) {
> +               /* Must wait for vblank to avoid spurious PCH FIFO underruns */
> +               intel_wait_for_vblank(dev, pipe);
> +               intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
> +       }
>  }
>
>  /* IPS only exists on ULT machines and is tied to pipe A. */
> @@ -5040,15 +5045,15 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>         int pipe = intel_crtc->pipe;
>         u32 reg, temp;
>
> +       if (intel_crtc->config->has_pch_encoder)
> +               intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
> +
>         for_each_encoder_on_crtc(dev, crtc, encoder)
>                 encoder->disable(encoder);
>
>         drm_crtc_vblank_off(crtc);
>         assert_vblank_disabled(crtc);
>
> -       if (intel_crtc->config->has_pch_encoder)
> -               intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
> -
>         intel_disable_pipe(intel_crtc);
>
>         ironlake_pfit_disable(intel_crtc, false);
> --
> 2.4.10
>
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-- 
Paulo Zanoni