[Intel-gfx] [PATCH 8/9] drm/i915: Android sync points for i915 v4 (obsolete)
Jesse Barnes
jbarnes at virtuousgeek.org
Fri Sep 4 09:59:02 PDT 2015
Allow for sync point exposure in the i915 driver. This
There are a couple of goals here:
1) allow applications and libraries to create fences without an
associated buffer
2) re-use a common API so userspace doesn't have to impedance mismatch
between different driver implementations too much
3) allow applications and libraries to use explicit synchronization if
they choose by exposing fences directly
v2: use struct fence directly using Maarten's new interface
v3: use new i915 request structure (Jesse)
make i915 fences a compile time option since Android support is still
in staging (Jesse)
check for request complete after arming IRQs (Chris)
v4: "fix" for latest requeset handling changes, request fences (Jesse)
Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
drivers/gpu/drm/i915/Kconfig | 14 ++
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.h | 20 +++
drivers/gpu/drm/i915/i915_gem.c | 4 +
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_sync.c | 334 +++++++++++++++++++++++++++++++++++++++
6 files changed, 376 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_sync.c
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 051eab3..8176aa1 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -36,6 +36,20 @@ config DRM_I915
i810 driver instead, and the Atom z5xx series has an entirely
different implementation.
+config DRM_I915_SYNC
+ bool "Enable explicit sync support"
+ depends on DRM_I915
+ depends on STAGING
+ depends on ANDROID
+ depends on SYNC
+ default y
+ help
+ Choose this option to enable Android native sync support and the
+ corresponding i915 driver code to expose it. Slightly increases
+ driver size and pulls in sync support from staging.
+
+ If in doubt, say "Y".
+
config DRM_I915_PRELIMINARY_HW_SUPPORT
bool "Enable preliminary support for prerelease Intel hardware by default"
depends on DRM_I915
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e4883a7..5a1f260 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -68,6 +68,7 @@ i915-y += intel_audio.o \
intel_sprite.o
i915-$(CONFIG_ACPI) += intel_acpi.o intel_opregion.o
i915-$(CONFIG_DRM_FBDEV_EMULATION) += intel_fbdev.o
+i915-$(CONFIG_DRM_I915_SYNC) += i915_sync.o
# modesetting output/encoder code
i915-y += dvo_ch7017.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f4a363d..0c3047b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1736,6 +1736,8 @@ struct i915_execbuffer_params {
struct drm_i915_gem_request *request;
};
+struct i915_sync_timeline;
+
struct drm_i915_private {
struct drm_device *dev;
struct kmem_cache *objects;
@@ -1781,6 +1783,9 @@ struct drm_i915_private {
uint32_t last_seqno, next_seqno;
struct drm_dma_handle *status_page_dmah;
+
+ struct i915_sync_timeline *sync_tl[I915_NUM_RINGS];
+
struct resource mch_res;
/* protects the irq masks */
@@ -2850,6 +2855,21 @@ void i915_gem_vma_destroy(struct i915_vma *vma);
#define PIN_USER (1<<4)
#define PIN_UPDATE (1<<5)
#define PIN_OFFSET_MASK (~4095)
+
+/* i915_sync.c */
+#ifdef CONFIG_DRM_I915_SYNC
+int i915_sync_init(struct drm_i915_private *dev_priv);
+void i915_sync_fini(struct drm_i915_private *dev_priv);
+int i915_sync_create_fence_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file);
+#else
+static inline int i915_sync_init(struct drm_i915_private *dev_priv)
+{
+ return 0;
+}
+static inline void i915_sync_fini(struct drm_i915_private *dev_priv) { }
+#endif
+
int __must_check
i915_gem_object_pin(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5341591..6fe6a42 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4813,6 +4813,8 @@ int i915_gem_init(struct drm_device *dev)
ret = 0;
}
+ i915_sync_init(dev_priv);
+
out_unlock:
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(&dev->struct_mutex);
@@ -4949,6 +4951,8 @@ void i915_gem_release(struct drm_device *dev, struct drm_file *file)
list_del(&file_priv->rps.link);
spin_unlock(&to_i915(dev)->rps.client_lock);
}
+
+ i915_sync_fini(dev->dev_private);
}
int i915_gem_open(struct drm_device *dev, struct drm_file *file)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 192ad0c..2a28d43 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -33,6 +33,7 @@
#include <linux/circ_buf.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
+#include "../../../staging/android/sync.h"
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
@@ -2311,8 +2312,9 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
*/
/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
- for_each_ring(ring, dev_priv, i)
+ for_each_ring(ring, dev_priv, i) {
wake_up_all(&ring->irq_queue);
+ }
/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
wake_up_all(&dev_priv->pending_flip_queue);
diff --git a/drivers/gpu/drm/i915/i915_sync.c b/drivers/gpu/drm/i915/i915_sync.c
new file mode 100644
index 0000000..46cea44
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_sync.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Jesse Barnes <jbarnes at virtuousgeek.org>
+ *
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_vma_manager.h>
+#include <drm/i915_drm.h>
+#include "i915_drv.h"
+#include "i915_trace.h"
+#include "intel_drv.h"
+#include <linux/oom.h>
+#include <linux/shmem_fs.h>
+#include <linux/slab.h>
+#include <linux/swap.h>
+#include <linux/pci.h>
+#include <linux/dma-buf.h>
+#include "../../../staging/android/sync.h"
+
+/* Nothing really to protect here... */
+static spinlock_t fence_lock;
+
+struct i915_sync_timeline {
+ struct sync_timeline base;
+ struct intel_engine_cs *ring;
+};
+
+/*
+ * i915 fences on sync timelines
+ *
+ * We implement sync points in terms of i915 seqnos. They're exposed
+ * through the new DRM_I915_GEM_FENCE ioctl, and can be mixed and matched
+ * with other Android timelines and aggregated into sync_fences, etc.
+ *
+ * TODO:
+ * allow non-RCS fences (need ring/context association)
+ */
+
+#define to_i915_request(x) container_of(x, struct drm_i915_gem_request, fence)
+
+static const char *i915_fence_get_driver_name(struct fence *fence)
+{
+ return "i915";
+}
+
+static const char *i915_fence_ring_get_timeline_name(struct fence *fence)
+{
+ struct drm_i915_gem_request *req = to_i915_request(fence);
+
+ return req->ring->name;
+}
+
+static int i915_fence_ring_check(wait_queue_t *wait, unsigned mode, int flags,
+ void *key)
+{
+ struct drm_i915_gem_request *req = wait->private;
+ struct intel_engine_cs *ring = req->ring;
+
+ if (!i915_gem_request_completed(req, false))
+ return 0;
+
+ fence_signal_locked(&req->fence);
+
+ __remove_wait_queue(&ring->irq_queue, wait);
+ fence_put(&req->fence);
+ ring->irq_put(ring);
+
+ return 0;
+}
+
+static bool i915_fence_ring_enable_signaling(struct fence *fence)
+{
+ struct drm_i915_gem_request *req = to_i915_request(fence);
+ struct intel_engine_cs *ring = req->ring;
+ struct drm_i915_private *dev_priv = ring->dev->dev_private;
+ wait_queue_t *wait = &req->wait;
+
+ /* queue fence wait queue on irq queue and get fence */
+ if (i915_gem_request_completed(req, false) ||
+ i915_terminally_wedged(&dev_priv->gpu_error))
+ return false;
+
+ if (!ring->irq_get(ring))
+ return false;
+
+ if (i915_gem_request_completed(req, false)) {
+ ring->irq_put(ring);
+ return true;
+ }
+
+ wait->flags = 0;
+ wait->private = req;
+ wait->func = i915_fence_ring_check;
+
+ __add_wait_queue(&ring->irq_queue, wait);
+ fence_get(fence);
+
+ return true;
+}
+
+static bool i915_fence_ring_signaled(struct fence *fence)
+{
+ struct drm_i915_gem_request *req = to_i915_request(fence);
+
+ return i915_gem_request_completed(req, false);
+}
+
+static signed long i915_fence_ring_wait(struct fence *fence, bool intr,
+ signed long timeout_js)
+{
+ struct drm_i915_gem_request *req = to_i915_request(fence);
+ struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
+ int ret;
+ s64 timeout;
+
+ timeout = jiffies_to_nsecs(timeout_js);
+
+ ret = __i915_wait_request(req,
+ atomic_read(&dev_priv->gpu_error.reset_counter),
+ intr, &timeout, NULL);
+ if (ret == -ETIME)
+ return nsecs_to_jiffies(timeout);
+
+ return ret;
+}
+
+static int i915_fence_ring_fill_driver_data(struct fence *fence, void *data,
+ int size)
+{
+ struct drm_i915_gem_request *req = to_i915_request(fence);
+
+ if (size < sizeof(req->seqno))
+ return -ENOMEM;
+
+ memcpy(data, &req->seqno,
+ sizeof(req->seqno));
+
+ return sizeof(req->seqno);
+}
+
+static void i915_fence_ring_value_str(struct fence *fence, char *str, int size)
+{
+ struct drm_i915_gem_request *req = to_i915_request(fence);
+
+ snprintf(str, size, "%u", req->seqno);
+}
+
+static void i915_fence_ring_timeline_value_str(struct fence *fence, char *str,
+ int size)
+{
+ struct drm_i915_gem_request *req = to_i915_request(fence);
+ struct intel_engine_cs *ring = req->ring;
+
+ snprintf(str, size, "%u", ring->get_seqno(ring, false));
+}
+
+static struct fence_ops i915_fence_ring_ops = {
+ .get_driver_name = i915_fence_get_driver_name,
+ .get_timeline_name = i915_fence_ring_get_timeline_name,
+ .enable_signaling = i915_fence_ring_enable_signaling,
+ .signaled = i915_fence_ring_signaled,
+ .wait = i915_fence_ring_wait,
+ .fill_driver_data = i915_fence_ring_fill_driver_data,
+ .fence_value_str = i915_fence_ring_value_str,
+ .timeline_value_str = i915_fence_ring_timeline_value_str,
+};
+
+static struct fence *i915_fence_create_ring(struct intel_engine_cs *ring,
+ struct intel_context *ctx)
+{
+ struct drm_i915_private *dev_priv = ring->dev->dev_private;
+ struct drm_i915_gem_request *request;
+ struct intel_ringbuffer *ringbuf;
+ u32 request_start;
+ int ret;
+
+ ret = i915_gem_request_alloc(ring, ctx, &request);
+ if (ret)
+ return ERR_PTR(ret);
+
+ if (i915.enable_execlists) {
+ ringbuf = ctx->engine[ring->id].ringbuf;
+ } else
+ ringbuf = ring->buffer;
+
+ request_start = intel_ring_get_tail(ringbuf);
+ /*
+ * Emit any outstanding flushes - execbuf can fail to emit the flush
+ * after having emitted the batchbuffer command. Hence we need to fix
+ * things up similar to emitting the lazy request. The difference here
+ * is that the flush _must_ happen before the next request, no matter
+ * what.
+ */
+ if (i915.enable_execlists)
+ ret = logical_ring_flush_all_caches(request);
+ else
+ ret = intel_ring_flush_all_caches(request);
+
+ if (ret) {
+ ret = -EIO;
+ goto err_cancel;
+ }
+
+ /* Record the position of the start of the request so that
+ * should we detect the updated seqno part-way through the
+ * GPU processing the request, we never over-estimate the
+ * position of the head.
+ */
+ request->postfix = intel_ring_get_tail(ringbuf);
+
+ if (i915.enable_execlists)
+ ret = ring->emit_request(request);
+ else
+ ret = ring->add_request(request);
+
+ if (ret) {
+ ret = -EIO;
+ goto err_cancel;
+ }
+
+ request->head = request_start;
+ request->tail = intel_ring_get_tail(ringbuf);
+ request->batch_obj = NULL;
+
+ request->emitted_jiffies = jiffies;
+ list_add_tail(&request->list, &ring->request_list);
+ request->file_priv = NULL;
+
+#if 0
+ if (file) {
+ struct drm_i915_file_private *file_priv = file->driver_priv;
+
+ spin_lock(&file_priv->mm.lock);
+ request->file_priv = file_priv;
+ list_add_tail(&request->client_list,
+ &file_priv->mm.request_list);
+ spin_unlock(&file_priv->mm.lock);
+
+ request->pid = get_pid(task_pid(current));
+ }
+#endif
+
+ i915_queue_hangcheck(ring->dev);
+
+ cancel_delayed_work_sync(&dev_priv->mm.idle_work);
+ queue_delayed_work(dev_priv->wq,
+ &dev_priv->mm.retire_work,
+ round_jiffies_up_relative(HZ));
+ intel_mark_busy(dev_priv->dev);
+
+ fence_init(&request->fence, &i915_fence_ring_ops, &fence_lock,
+ ctx->user_handle, request->seqno);
+
+ return &request->fence;
+
+err_cancel:
+ i915_gem_request_cancel(request);
+
+ return ERR_PTR(ret);
+}
+
+#if 0
+static struct fence_ops i915_fence_display_ops = {
+ .get_driver_name = i915_fence_get_driver_name,
+ .get_timeline_name = i915_fence_display_get_timeline_name,
+ .enable_signaling = i915_fence_display_enable_signaling,
+ .signaled = i915_fence_display_signaled,
+ .wait = i915_fence_display_wait,
+ .fill_driver_data = i915_fence_display_fill_driver_data,
+ .fence_value_str = i915_fence_display_value_str,
+ .timeline_value_str = i915_fence_display_timeline_value_str,
+};
+
+static struct fence *i915_fence_create_display(struct intel_context *ctx)
+{
+ struct drm_i915_gem_request *req;
+ int ret;
+
+ ret = ring->add_request(ring);
+ if (ret) {
+ DRM_ERROR("add_request failed\n");
+ return NULL;
+ }
+
+ req = ring->outstanding_lazy_request;
+
+ fence_init(&req->fence, &i915_fence_ops, &fence_lock,
+ ctx->user_handle, req->seqno);
+
+ return &req->fence;
+}
+#endif
+
+int i915_sync_init(struct drm_i915_private *dev_priv)
+{
+ struct intel_engine_cs *ring;
+ int i, ret = 0;
+
+ for_each_ring(ring, dev_priv, i) {
+ /* FIXME: non-RCS fences */
+ }
+
+ return ret;
+}
+
+void i915_sync_fini(struct drm_i915_private *dev_priv)
+{
+ int i;
+
+ for (i = 0; i < I915_NUM_RINGS; i++) {
+ }
+}
--
1.9.1
More information about the Intel-gfx
mailing list