[Intel-gfx] [PATCH] drm/i915: Make sure fb objects with rotated views are also fenceable
Vivek Kasireddy
vivek.kasireddy at intel.com
Fri Sep 11 18:44:26 PDT 2015
From: Vivek Kasireddy <vivek.kasireddy at intel.com>
Currently, fb objects with rotated views are ignored while pinning. Therefore,
include the rotated view type and use the view size instead of the object's
size to determine if it is fenceable. And, look at the view and its offset
while writing and pinning to the fence registers.
Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
Cc: Matthew D Roper <matthew.d.roper at intel.com>
Signed-off-by: Vivek Kasireddy <vivek.kasireddy at intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++--
drivers/gpu/drm/i915/i915_gem.c | 13 +++++----
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +--
drivers/gpu/drm/i915/i915_gem_fence.c | 47 ++++++++++++++++++++----------
drivers/gpu/drm/i915/intel_display.c | 4 +--
5 files changed, 48 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index df37e88..9bd8d11 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3101,10 +3101,12 @@ i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
}
/* i915_gem_fence.c */
-int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
+int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
+ const struct i915_ggtt_view *view);
int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
-bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
+bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj,
+ const struct i915_ggtt_view *view);
void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
void i915_gem_restore_fences(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 41263cd..c0c3441 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1789,7 +1789,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
if (ret)
goto unpin;
- ret = i915_gem_object_get_fence(obj);
+ ret = i915_gem_object_get_fence(obj, NULL);
if (ret)
goto unpin;
@@ -4054,16 +4054,19 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
return ret;
}
- if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
+ if (ggtt_view && (ggtt_view->type == I915_GGTT_VIEW_NORMAL ||
+ ggtt_view->type == I915_GGTT_VIEW_ROTATED) &&
(bound ^ vma->bound) & GLOBAL_BIND) {
bool mappable, fenceable;
- u32 fence_size, fence_alignment;
+ u32 fence_size, fence_alignment, view_size;
+
+ view_size = i915_ggtt_view_size(obj, ggtt_view);
fence_size = i915_gem_get_gtt_size(obj->base.dev,
- obj->base.size,
+ view_size,
obj->tiling_mode);
fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
- obj->base.size,
+ view_size,
obj->tiling_mode,
true);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a953d49..1566f88 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -608,11 +608,11 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
entry->flags |= __EXEC_OBJECT_HAS_PIN;
if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
- ret = i915_gem_object_get_fence(obj);
+ ret = i915_gem_object_get_fence(obj, NULL);
if (ret)
return ret;
- if (i915_gem_object_pin_fence(obj))
+ if (i915_gem_object_pin_fence(obj, NULL))
entry->flags |= __EXEC_OBJECT_HAS_FENCE;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index 6077dff..336ebee 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -56,11 +56,13 @@
*/
static void i965_write_fence_reg(struct drm_device *dev, int reg,
- struct drm_i915_gem_object *obj)
+ struct drm_i915_gem_object *obj,
+ const struct i915_ggtt_view *view)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int fence_reg;
int fence_pitch_shift;
+ const struct i915_ggtt_view *ggtt_view = view;
if (INTEL_INFO(dev)->gen >= 6) {
fence_reg = FENCE_REG_SANDYBRIDGE_0;
@@ -95,9 +97,13 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
size = (size / row_size) * row_size;
}
- val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
- 0xfffff000) << 32;
- val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
+ if (!ggtt_view)
+ ggtt_view = &i915_ggtt_view_normal;
+
+ val = (uint64_t)((i915_gem_obj_ggtt_offset_view((obj), ggtt_view)
+ + size - 4096) & 0xfffff000) << 32;
+ val |= i915_gem_obj_ggtt_offset_view((obj), ggtt_view) & 0xfffff000;
+
val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
if (obj->tiling_mode == I915_TILING_Y)
val |= 1 << I965_FENCE_TILING_Y_SHIFT;
@@ -196,7 +202,8 @@ inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
}
static void i915_gem_write_fence(struct drm_device *dev, int reg,
- struct drm_i915_gem_object *obj)
+ struct drm_i915_gem_object *obj,
+ const struct i915_ggtt_view *view)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -215,7 +222,7 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg,
else if (IS_GEN3(dev))
i915_write_fence_reg(dev, reg, obj);
else if (INTEL_INFO(dev)->gen >= 4)
- i965_write_fence_reg(dev, reg, obj);
+ i965_write_fence_reg(dev, reg, obj, view);
/* And similarly be paranoid that no direct access to this region
* is reordered to before the fence is installed.
@@ -232,12 +239,13 @@ static inline int fence_number(struct drm_i915_private *dev_priv,
static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
struct drm_i915_fence_reg *fence,
- bool enable)
+ bool enable,
+ const struct i915_ggtt_view *view)
{
struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
int reg = fence_number(dev_priv, fence);
- i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
+ i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL, view);
if (enable) {
obj->fence_reg = reg;
@@ -308,7 +316,7 @@ i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
return -EBUSY;
i915_gem_object_fence_lost(obj);
- i915_gem_object_update_fence(obj, fence, false);
+ i915_gem_object_update_fence(obj, fence, false, NULL);
return 0;
}
@@ -369,7 +377,8 @@ deadlock:
* 0 on success, negative error code on failure.
*/
int
-i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
+i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
+ const struct i915_ggtt_view *view)
{
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -414,7 +423,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
} else
return 0;
- i915_gem_object_update_fence(obj, reg, enable);
+ i915_gem_object_update_fence(obj, reg, enable, view);
return 0;
}
@@ -435,11 +444,18 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
* True if the object has a fence, false otherwise.
*/
bool
-i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
+i915_gem_object_pin_fence(struct drm_i915_gem_object *obj,
+ const struct i915_ggtt_view *view)
{
if (obj->fence_reg != I915_FENCE_REG_NONE) {
struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
- struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
+ const struct i915_vma *ggtt_vma;
+
+ if (view)
+ ggtt_vma = i915_gem_obj_to_ggtt_view(obj, view);
+ else
+ ggtt_vma = i915_gem_obj_to_ggtt_view(obj,
+ &i915_ggtt_view_normal);
WARN_ON(!ggtt_vma ||
dev_priv->fence_regs[obj->fence_reg].pin_count >
@@ -489,9 +505,10 @@ void i915_gem_restore_fences(struct drm_device *dev)
*/
if (reg->obj) {
i915_gem_object_update_fence(reg->obj, reg,
- reg->obj->tiling_mode);
+ reg->obj->tiling_mode,
+ NULL);
} else {
- i915_gem_write_fence(dev, i, NULL);
+ i915_gem_write_fence(dev, i, NULL, NULL);
}
}
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 52fb3f2..b77074f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2357,7 +2357,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
* framebuffer compression. For simplicity, we always install
* a fence as the cost is not that onerous.
*/
- ret = i915_gem_object_get_fence(obj);
+ ret = i915_gem_object_get_fence(obj, &view);
if (ret == -EDEADLK) {
/*
* -EDEADLK means there are no free fences
@@ -2372,7 +2372,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
} else if (ret)
goto err_unpin;
- i915_gem_object_pin_fence(obj);
+ i915_gem_object_pin_fence(obj, &view);
dev_priv->mm.interruptible = true;
intel_runtime_pm_put(dev_priv);
--
2.4.3
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