[Intel-gfx] [PATCH 5/6] drm/i915/gen9: WA ST Unit Power Optimization Disable

[Kamble, Sagar A]

Reviewed-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>

On 9/14/2015 2:55 PM, Arun Siluvery wrote:
> On 12/09/2015 17:52, Kamble, Sagar A wrote:
>>
>>
>> On 9/8/2015 3:01 PM, Arun Siluvery wrote:
>>> From: Robert Beckett <robert.beckett at intel.com>
>>>
>>> WaDisableSTUnitPowerOptimization:skl,bxt
>>>
>>> Signed-off-by: Robert Beckett <robert.beckett at intel.com>
>>> Signed-off-by: Arun Siluvery <arun.siluvery at linux.intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/i915_reg.h         | 3 +++
>>>   drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>>>   2 files changed, 6 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> b/drivers/gpu/drm/i915/i915_reg.h
>>> index 2c719b0..9b47dd4 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -6940,6 +6940,9 @@ enum skl_disp_power_wells {
>>>   #define HSW_ROW_CHICKEN3        0xe49c
>>>   #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
>>> +#define HALF_SLICE_CHICKEN2        0xe180
>>> +#define   GEN8_ST_PO_DISABLE        (1<<13)
>> Can we name this as GEN9_STUNIT_PO_DISABLE, since this does not apply on
>> GEN8?
>
> According to the spec this bit is applicable for BDW also so Gen8 
> should be ok.
>
> regards
> Arun
>
>> With that: Reviewed-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
>>> +
>>>   #define HALF_SLICE_CHICKEN3        0xe184
>>>   #define   HSW_SAMPLE_C_PERFORMANCE    (1<<9)
>>>   #define   GEN8_CENTROID_PIXEL_OPT_DIS    (1<<8)
>>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> index 0e1ed0b..028c099 100644
>>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> @@ -990,6 +990,9 @@ static int gen9_init_workarounds(struct
>>> intel_engine_cs *ring)
>>>                     GEN8_SAMPLER_POWER_BYPASS_DIS);
>>>       }
>>> +    /* WaDisableSTUnitPowerOptimization:skl,bxt */
>>> +    WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>>> +
>>>       return 0;
>>>   }
>>
>>
>