[Intel-gfx] [PATCH 06/43] drm/i915: Parametrize ILK turbo registers

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
>  drivers/gpu/drm/i915/intel_pm.c | 14 +++++++-------
>  2 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fcd1e81..b95f7f1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2576,7 +2576,7 @@ enum skl_disp_power_wells {
>  #define   TSFS_INTR_MASK	0x000000ff
>  
>  #define CRSTANDVID		0x11100
> -#define PXVFREQ_BASE		0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
> +#define PXVFREQ(i)		(0x11110 + (i) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
>  #define   PXVFREQ_PX_MASK	0x7f000000
>  #define   PXVFREQ_PX_SHIFT	24
>  #define VIDFREQ_BASE		0x11110
> @@ -2760,8 +2760,8 @@ enum skl_disp_power_wells {
>  #define CSIEW0			0x11250
>  #define CSIEW1			0x11254
>  #define CSIEW2			0x11258
> -#define PEW			0x1125c
> -#define DEW			0x11270
> +#define PEW(i)			(0x1125c + (i) * 4) /* 5 registers */
> +#define DEW(i)			(0x11270 + (i) * 4) /* 3 registers */
>  #define MCHAFE			0x112c0
>  #define CSIEC			0x112e0
>  #define DMIEC			0x112e4
> @@ -2785,8 +2785,8 @@ enum skl_disp_power_wells {
>  #define EG5			0x11624
>  #define EG6			0x11628
>  #define EG7			0x1162c
> -#define PXW			0x11664
> -#define PXWL			0x11680
> +#define PXW(i)			(0x11664 + (i) * 4) /* 4 registers */
> +#define PXWL(i)			(0x11680 + (i) * 4) /* 8 registers */
>  #define LCFUSE02		0x116c0
>  #define   LCFUSE_HIV_MASK	0x000000ff
>  #define CSIPLL0			0x12c10
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 62de97e..0320675 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4274,7 +4274,7 @@ static void ironlake_enable_drps(struct drm_device *dev)
>  	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
>  		MEMMODE_FSTART_SHIFT;
>  
> -	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
> +	vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
>  		PXVFREQ_PX_SHIFT;
>  
>  	dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
> @@ -5877,7 +5877,7 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
>  
>  	assert_spin_locked(&mchdev_lock);
>  
> -	pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
> +	pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
>  	pxvid = (pxvid >> 24) & 0x7f;
>  	ext_v = pvid_to_extvid(dev_priv, pxvid);
>  
> @@ -6120,13 +6120,13 @@ static void intel_init_emon(struct drm_device *dev)
>  	I915_WRITE(CSIEW2, 0x04000004);
>  
>  	for (i = 0; i < 5; i++)
> -		I915_WRITE(PEW + (i * 4), 0);
> +		I915_WRITE(PEW(i), 0);
>  	for (i = 0; i < 3; i++)
> -		I915_WRITE(DEW + (i * 4), 0);
> +		I915_WRITE(DEW(i), 0);
>  
>  	/* Program P-state weights to account for frequency power adjustment */
>  	for (i = 0; i < 16; i++) {
> -		u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
> +		u32 pxvidfreq = I915_READ(PXVFREQ(i));
>  		unsigned long freq = intel_pxfreq(pxvidfreq);
>  		unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
>  			PXVFREQ_PX_SHIFT;
> @@ -6147,7 +6147,7 @@ static void intel_init_emon(struct drm_device *dev)
>  	for (i = 0; i < 4; i++) {
>  		u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
>  			(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
> -		I915_WRITE(PXW + (i * 4), val);
> +		I915_WRITE(PXW(i), val);
>  	}
>  
>  	/* Adjust magic regs to magic values (more experimental results) */
> @@ -6163,7 +6163,7 @@ static void intel_init_emon(struct drm_device *dev)
>  	I915_WRITE(EG7, 0);
>  
>  	for (i = 0; i < 8; i++)
> -		I915_WRITE(PXWL + (i * 4), 0);
> +		I915_WRITE(PXWL(i), 0);
>  
>  	/* Enable PMON + select events */
>  	I915_WRITE(ECR, 0x80000019);
> -- 
> 2.4.6
>
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-- 
Jani Nikula, Intel Open Source Technology Center