[Intel-gfx] [PATCH 3/5] drm/i915: WaRsDisableCoarsePowerGating

[Daniel Vetter]

On Mon, Sep 21, 2015 at 09:43:49AM -0700, Yu Dai wrote:
> 
> 
> On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
> >WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
> >disabled for platforms prior to BXT B0 and till SKL E0.
> >
> >Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
> >Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
> >---
> >  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
> >  1 file changed, 7 insertions(+), 4 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >index 75f1c8c..c0345d2 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -4840,11 +4840,14 @@ static void gen9_enable_rc6(struct drm_device *dev)
> >  	/*
> >  	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> >-	 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
> >+	 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
> >  	 */
> >-	I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> >-			GEN9_MEDIA_PG_ENABLE : 0);
> >-
> >+	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> >+		(IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> >+		I915_WRITE(GEN9_PG_ENABLE, 0);
> >+	else
> >+		I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> >+				(GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
> >  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> 
> Reviewed by: Alex Dai <yu.dai at intel.com>.

You reviewed an old version of this patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch