[Intel-gfx] [PATCH v2 3/7] drm/i915: WaRsUseTimeoutMode

[Daniel Vetter]

On Sat, Sep 12, 2015 at 10:17:52AM +0530, Sagar Arun Kamble wrote:
> Enable TO mode for RC6 for SKL till D0 and BXT till A0.
> 
> Cc: Tom O'Rourke <Tom.O'Rourke at intel.com>
> Cc: Akash Goel <akash.goel at intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c93d3a7..6e4818d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4847,9 +4847,16 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
>  	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
>  			"on" : "off");
> -	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> -				   GEN6_RC_CTL_EI_MODE(1) |
> -				   rc6_mask);
> +
> +	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
> +		(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))

Again I fixed the continuation alignment here ...
-Daniel

> +                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> +                                GEN7_RC_CTL_TO_MODE |
> +                                rc6_mask);
> +        else
> +                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> +                                GEN6_RC_CTL_EI_MODE(1) |
> +                                rc6_mask);
>  
>  	/*
>  	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> -- 
> 1.9.1
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch