[Intel-gfx] [PATCH v2 1/6] drm/i915/guc: Fix a bug in GuC status check

[Daniel Vetter]

On Thu, Sep 24, 2015 at 10:29:18AM +0530, Kamble, Sagar A wrote:
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
> 
> On 9/23/2015 2:18 AM, yu.dai at intel.com wrote:
> >From: Alex Dai <yu.dai at intel.com>
> >
> >Bit 16 of GuC status indicates resuming from RC6. The LAPIC_DONE
> >status is a reliable readiness flag only when resuming from RC6.
> >This fix a racing issue that allocation of doorbell fails whilst
> >GuC init is not finished.
> >
> >Signed-off-by: Alex Dai <yu.dai at intel.com>

Queued for -next, thanks for the patch.
-Daniel
> >---
> >  drivers/gpu/drm/i915/i915_guc_reg.h     | 1 +
> >  drivers/gpu/drm/i915/intel_guc_loader.c | 5 +++--
> >  2 files changed, 4 insertions(+), 2 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> >index 8c8e574..dd0e1e8 100644
> >--- a/drivers/gpu/drm/i915/i915_guc_reg.h
> >+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> >@@ -37,6 +37,7 @@
> >  #define   GS_UKERNEL_READY		  (0xF0 << GS_UKERNEL_SHIFT)
> >  #define   GS_MIA_SHIFT			16
> >  #define   GS_MIA_MASK			  (0x07 << GS_MIA_SHIFT)
> >+#define   GS_MIA_CORE_STATE		  (1 << GS_MIA_SHIFT)
> >  #define SOFT_SCRATCH(n)			(0xc180 + ((n) * 4))
> >diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> >index e0601cc..40241f3 100644
> >--- a/drivers/gpu/drm/i915/intel_guc_loader.c
> >+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> >@@ -209,9 +209,10 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
> >  				      u32 *status)
> >  {
> >  	u32 val = I915_READ(GUC_STATUS);
> >+	u32 uk_val = val & GS_UKERNEL_MASK;
> >  	*status = val;
> >-	return ((val & GS_UKERNEL_MASK) == GS_UKERNEL_READY ||
> >-		(val & GS_UKERNEL_MASK) == GS_UKERNEL_LAPIC_DONE);
> >+	return (uk_val == GS_UKERNEL_READY ||
> >+		((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
> >  }
> >  /*
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch