[Intel-gfx] [PATCH 3/4] drm/i915: Simplify vlv/chv rc6 residency calculation
Imre Deak
imre.deak at intel.com
Mon Sep 28 12:37:52 PDT 2015
On Thu, 2015-09-24 at 23:29 +0300, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> We have the czclk freqeuency in dev_priv now, so let's just use it
^frequency
> when converting the rc6 counters to milliseconds. This elimiantes
^eliminates
> a bunch of hairy code that essentially tries to extract the czclk
> frequency using yet another method.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Imre Deak <imre.deak at intel.com>
> ---
> drivers/gpu/drm/i915/i915_sysfs.c | 31 +++----------------------------
> 1 file changed, 3 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 55bd04c..74086eb 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -39,7 +39,7 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> u64 raw_time; /* 32b value may overflow during fixed point math */
> - u64 units = 128ULL, div = 100000ULL, bias = 100ULL;
> + u64 units = 128ULL, div = 100000ULL;
> u32 ret;
>
> if (!intel_enable_rc6(dev))
> @@ -49,41 +49,16 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg)
>
> /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
> if (IS_VALLEYVIEW(dev)) {
> - u32 clk_reg, czcount_30ns;
> -
> - if (IS_CHERRYVIEW(dev))
> - clk_reg = CHV_CLK_CTL1;
> - else
> - clk_reg = VLV_CLK_CTL2;
> -
> - czcount_30ns = I915_READ(clk_reg) >> CLK_CTL2_CZCOUNT_30NS_SHIFT;
> -
> - if (!czcount_30ns) {
> - WARN(!czcount_30ns, "bogus CZ count value");
> - ret = 0;
> - goto out;
> - }
> -
> - if (IS_CHERRYVIEW(dev) && czcount_30ns == 1) {
> - /* Special case for 320Mhz */
> - div = 10000000ULL;
> - units = 3125ULL;
> - } else {
> - czcount_30ns += 1;
> - div = 1000000ULL;
> - units = DIV_ROUND_UP_ULL(30ULL * bias, czcount_30ns);
> - }
> + units = 1;
> + div = dev_priv->czclk_freq;
>
> if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
> units <<= 8;
> -
> - div = div * bias;
> }
>
> raw_time = I915_READ(reg) * units;
> ret = DIV_ROUND_UP_ULL(raw_time, div);
>
> -out:
> intel_runtime_pm_put(dev_priv);
> return ret;
> }
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