[Intel-gfx] [PATCH 18/43] drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>


> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++----
>  drivers/gpu/drm/i915/intel_pm.c      | 4 ++--
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7343e14..63cf5eb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2003,9 +2003,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>  	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
>  
>  	/* Workaround: set timing override bit. */
> -	val = I915_READ(_TRANSA_CHICKEN2);
> +	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
>  	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> -	I915_WRITE(_TRANSA_CHICKEN2, val);
> +	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
>  
>  	val = TRANS_ENABLE;
>  	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
> @@ -2063,9 +2063,9 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
>  		DRM_ERROR("Failed to disable PCH transcoder\n");
>  
>  	/* Workaround: clear timing override bit. */
> -	val = I915_READ(_TRANSA_CHICKEN2);
> +	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
>  	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
> -	I915_WRITE(_TRANSA_CHICKEN2, val);
> +	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index dc765eb..0d43d51 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6623,8 +6623,8 @@ static void lpt_init_clock_gating(struct drm_device *dev)
>  			   PCH_LP_PARTITION_LEVEL_DISABLE);
>  
>  	/* WADPOClockGatingDisable:hsw */
> -	I915_WRITE(_TRANSA_CHICKEN1,
> -		   I915_READ(_TRANSA_CHICKEN1) |
> +	I915_WRITE(TRANS_CHICKEN1(PIPE_A),
> +		   I915_READ(TRANS_CHICKEN1(PIPE_A)) |
>  		   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
>  }
>  
> -- 
> 2.4.6
>
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-- 
Jani Nikula, Intel Open Source Technology Center