[Intel-gfx] [PATCH 03/14] drm/i915: Add functions for dcs memory write cmd

[Gaurav K Singh]

Add functions for DCS memory write command. The mem write
command to send fb data to panel is sent using this function.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu at intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |    1 +
 drivers/gpu/drm/i915/intel_drv.h |    1 +
 drivers/gpu/drm/i915/intel_dsi.c |   41 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4e5c0bb..ccba984 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4334,6 +4334,7 @@ enum skl_disp_power_wells {
 #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
 #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
 #define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
+#define   PIPECONF_MIPI_DSR_ENABLE		(1 << 20)
 #define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
 #define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
 #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index dae3cfd..b3d16ce 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1219,6 +1219,7 @@ void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
 /* intel_dsi.c */
 void intel_dsi_init(struct drm_device *dev);
 
+void intel_dsi_update_panel_fb(struct intel_encoder *encoder);
 
 /* intel_dvo.c */
 void intel_dvo_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 6483d7f..8d018d0 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -33,6 +33,7 @@
 #include <linux/slab.h>
 #include <linux/gpio/consumer.h>
 #include <linux/dma-mapping.h>
+#include <video/mipi_display.h>
 #include "i915_drv.h"
 #include "intel_drv.h"
 #include "intel_dsi.h"
@@ -204,6 +205,38 @@ static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 	return host;
 }
 
+int dsi_send_dcs_cmd(struct intel_dsi *intel_dsi, int channel, const u8 *data,
+		     int len, bool pipe_render)
+{
+	struct drm_encoder *encoder = &intel_dsi->base.base;
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum port port;
+	u32 cmd_addr;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (I915_READ(MIPI_COMMAND_ADDRESS(port)) & COMMAND_VALID)
+			return -EBUSY;
+
+		if ((I915_READ(PIPECONF(port)) & PIPECONF_MIPI_DSR_ENABLE) == 0)
+			return -EBUSY;
+
+		if (IS_CHERRYVIEW(dev)) {
+			cmd_addr = intel_dsi->dma_handle &
+							COMMAND_MEM_ADDRESS_MASK;
+			cmd_addr |= COMMAND_VALID;
+
+			if (pipe_render)
+				cmd_addr |= MEMORY_WRITE_DATA_FROM_PIPE_RENDERING;
+		}
+
+		I915_WRITE(MIPI_COMMAND_LENGTH(port), len);
+		I915_WRITE(MIPI_COMMAND_ADDRESS(port), cmd_addr);
+	}
+
+	return 0;
+}
+
 /*
  * send a video mode command
  *
@@ -748,6 +781,14 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->port_clock = pclk;
 }
 
+void intel_dsi_update_panel_fb(struct intel_encoder *encoder)
+{
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	unsigned char uc_data[] = {MIPI_DCS_WRITE_MEMORY_START};
+
+	dsi_send_dcs_cmd(intel_dsi, 0, uc_data, sizeof(uc_data), true);
+}
+
 static enum drm_mode_status
 intel_dsi_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
-- 
1.7.9.5