[Intel-gfx] [PATCH 09/14] drm/i915: Changes for command mode preparation

[Gaurav K Singh]

Changes done in preparation of command mode-

1. Set DBI HS LS Switch bit for DBI packets to be tramitted in HS mode.
2. Set DBI FIFO watermark.
3. Timing regs need not be programmmed for command mode.

Signed-off-by: Gaurav K Singh <gaurav.k.singh at intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu at intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4a5905e..70c4e56 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -999,12 +999,16 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 			mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 	}
 
-	set_dsi_timings(encoder, adjusted_mode);
+	if (is_vid_mode(intel_dsi))
+		set_dsi_timings(encoder, adjusted_mode);
 
 	val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 	if (is_cmd_mode(intel_dsi)) {
 		val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
-		val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
+		val |= CMD_MODE_DATA_WIDTH_OPTION2;
+		I915_WRITE(MIPI_DBI_FIFO_THROTTLE(port),
+			   DBI_FIFO_EMPTY_QUARTER);
+		I915_WRITE(MIPI_HS_LP_DBI_ENABLE(port), 0);
 	} else {
 		val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 
@@ -1117,6 +1121,11 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 				intel_dsi->video_mode_format |
 				IP_TG_CONFIG |
 				RANDOM_DPI_DISPLAY_RESOLUTION);
+		else
+			I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
+				   intel_dsi->video_frmt_cfg_bits |
+				   IP_TG_CONFIG |
+				   RANDOM_DPI_DISPLAY_RESOLUTION);
 	}
 }
 
-- 
1.7.9.5