[Intel-gfx] [PATCH 19/43] drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.

[Ville Syrjälä]

On Wed, Sep 30, 2015 at 04:44:21PM +0300, Jani Nikula wrote:
> On Fri, 18 Sep 2015, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Reviewed-by: Jani Nikula <jani.nikula at intel.com>
> 
> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  4 ++--
> >  drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++--------
> >  2 files changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 93cb6ed..25864ae 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7401,8 +7401,8 @@ enum skl_disp_power_wells {
> >  #define  DPLL_CFGCR2_PDIV_7 (4<<2)
> >  #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
> >  
> > -#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
> > -#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
> > +#define DPLL_CFGCR1(id) (DPLL1_CFGCR1 + ((id) - SKL_DPLL1) * 8)
> > +#define DPLL_CFGCR2(id) (DPLL1_CFGCR2 + ((id) - SKL_DPLL1) * 8)
> >  
> >  /* BXT display engine PLL */
> >  #define BXT_DE_PLL_CTL			0x6d000
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index b885b70..399e70e 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -953,8 +953,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> >  	uint32_t cfgcr1_val, cfgcr2_val;
> >  	uint32_t p0, p1, p2, dco_freq;
> >  
> > -	cfgcr1_reg = GET_CFG_CR1_REG(dpll);
> > -	cfgcr2_reg = GET_CFG_CR2_REG(dpll);
> > +	cfgcr1_reg = DPLL_CFGCR1(dpll);
> > +	cfgcr2_reg = DPLL_CFGCR2(dpll);
> >  
> >  	cfgcr1_val = I915_READ(cfgcr1_reg);
> >  	cfgcr2_val = I915_READ(cfgcr2_reg);
> > @@ -2480,20 +2480,20 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
> >  	{
> >  		/* DPLL 1 */
> >  		.ctl = LCPLL2_CTL,
> > -		.cfgcr1 = DPLL1_CFGCR1,
> > -		.cfgcr2 = DPLL1_CFGCR2,
> > +		.cfgcr1 = DPLL_CFGCR1(1),
> > +		.cfgcr2 = DPLL_CFGCR2(1),
> >  	},
> >  	{
> >  		/* DPLL 2 */
> >  		.ctl = WRPLL_CTL1,
> > -		.cfgcr1 = DPLL2_CFGCR1,
> > -		.cfgcr2 = DPLL2_CFGCR2,
> > +		.cfgcr1 = DPLL_CFGCR1(2),
> > +		.cfgcr2 = DPLL_CFGCR2(2),
> >  	},
> >  	{
> >  		/* DPLL 3 */
> >  		.ctl = WRPLL_CTL2,
> > -		.cfgcr1 = DPLL3_CFGCR1,
> > -		.cfgcr2 = DPLL3_CFGCR2,
> > +		.cfgcr1 = DPLL_CFGCR1(3),
> > +		.cfgcr2 = DPLL_CFGCR2(3),

I guess I really should have used the SKL_DPLL names here. I think it
was me who even asked for them originally. Let me respin with that small
change...

> >  	},
> >  };
> >  
> > -- 
> > 2.4.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC