[Intel-gfx] [PATCH 00/16] drm/i915/bxt: Fix/enable display power well support/runtime PM

[Imre Deak]

This patchset works around/fixes a few DMC and PHY issues and enables
display power well support and runtime PM.

CC: Mika Kuoppala <mika.kuoppala at linux.intel.com>
CC: Patrik Jakobsson <patrik.jakobsson at linux.intel.com>
CC: Matt Ropert <matthew.d.roper at intel.com>

Imre Deak (16):
  drm/i915/bxt: Reject DMC firmware versions with known bugs
  drm/i915/bxt: Fix GRC code register field definitions
  drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only
  drm/i915/bxt: Reset secondary power well requests left on by DMC/KVMR
  drm/i915/gen9: Make power well disabling synchronous
  drm/i915/gen9: Fix DMC/DC state asserts
  drm/i915/bxt: Suspend power domains during suspend-to-idle
  drm/i915/skl: Unexport skl_pw1_misc_io_init
  drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers
  drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit
  drm/i915/bxt: Don't toggle power well 1 on-demand
  drm/i915/bxt: Sanitize the DBUF HW state together with CDCLK
  drm/i915/bxt: Don't reprogram an already enabled DDI PHY
  drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK
  Revert "drm/i915/bxt: Disable power well support"
  drm/i915/bxt: Enable runtime PM

 drivers/gpu/drm/i915/i915_drv.c         |  25 +---
 drivers/gpu/drm/i915/i915_drv.h         |   3 +-
 drivers/gpu/drm/i915/i915_reg.h         |   6 +-
 drivers/gpu/drm/i915/intel_csr.c        |  20 ++-
 drivers/gpu/drm/i915/intel_ddi.c        | 182 +++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_display.c    |  62 +++++----
 drivers/gpu/drm/i915/intel_dpll_mgr.c   |   5 +-
 drivers/gpu/drm/i915/intel_drv.h        |  14 ++-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 217 +++++++++++++++++++++-----------
 9 files changed, 384 insertions(+), 150 deletions(-)

-- 
2.5.0