[Intel-gfx] [PATCH 06/16] drm/i915: Remove the "three times for luck" trick from vlv_enable_pll()

[Ville Syrjälä]

On Wed, Mar 16, 2016 at 11:05:30AM +0200, Jani Nikula wrote:
> On Tue, 15 Mar 2016, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> >
> > VLV DPLL is somewhat sane and doesn't run on luck.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Acked-by: Jani Nikula <jani.nikula at intel.com>

Pushed to dinq up to this patch. Thanks for the review.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 11 -----------
> >  1 file changed, 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index d3332a33f8a7..c85b77c1188d 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1590,17 +1590,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
> >  
> >  	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
> >  	POSTING_READ(DPLL_MD(pipe));
> > -
> > -	/* We do this three times for luck */
> > -	I915_WRITE(reg, dpll);
> > -	POSTING_READ(reg);
> > -	udelay(150); /* wait for warmup */
> > -	I915_WRITE(reg, dpll);
> > -	POSTING_READ(reg);
> > -	udelay(150); /* wait for warmup */
> > -	I915_WRITE(reg, dpll);
> > -	POSTING_READ(reg);
> > -	udelay(150); /* wait for warmup */
> >  }
> >  
> >  static void chv_enable_pll(struct intel_crtc *crtc,
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC