[Intel-gfx] [PATCH 2/2] drm/i915/BXT: Get pipe conf from the port registers

[Ramalingam C]

Jani/Daniel,

I am working on implementing the pipe_config compare as suggested by 
daniel at 
https://lists.freedesktop.org/archives/intel-gfx/2016-March/091148.html

But I think this patch need not wait for that change. Either way this 
patch is required. We can continue review on this and proceed further.

On Wednesday 30 March 2016 07:23 PM, Ramalingam C wrote:
> At BXT DSI, PIPE registers are inactive. So we can't get the
> PIPE's mode parameters from them. The possible option is
> retriving them from the PORT registers.
>
> The required changes are added for BXT in intel_dsi_get_config
> (encoder->get_config).
>
> v2: Addressed the Jani's comments
>      -removed the redundant call to encoder->get_config
>      -read bpp from port register
>      -removed retrival of src_size from encoder->get_config
>
> Signed-off-by: Ramalingam C <ramalingam.c at intel.com>
> Signed-off-by: Uma Shankar <uma.shankar at intel.com>
> ---
> Previously reviewed at https://patchwork.freedesktop.org/patch/75301/
>
>   drivers/gpu/drm/i915/intel_dsi.c |   99 ++++++++++++++++++++++++++++++++++++++
>   1 file changed, 99 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 0de74e1..2117187 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -46,6 +46,11 @@ static const struct {
>   	},
>   };
>   
> +enum mipi_dsi_pixel_format reg_to_pixel_format(u32 fmt)
> +{
> +	return pixel_format_from_vbt(fmt);
> +}
> +
>   static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
>   {
>   	struct drm_encoder *encoder = &intel_dsi->base.base;
> @@ -740,14 +745,108 @@ out_put_power:
>   	return active;
>   }
>   
> +/* return pixels equvalent to txbyteclkhs */
> +static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
> +		       u16 burst_mode_ratio)
> +{
> +	return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
> +						(bpp * burst_mode_ratio));
> +}
> +
> +static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> +				 struct intel_crtc_state *pipe_config)
> +{
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_display_mode *adjusted_mode =
> +					&pipe_config->base.adjusted_mode;
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	unsigned int lane_count = intel_dsi->lane_count;
> +	unsigned int bpp, fmt;
> +	enum port port;
> +	u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
> +
> +	/*
> +	 * Atleast one port is active as encoder->get_config called only if
> +	 * encoder->get_hw_state() returns true.
> +	 */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (!(I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE))
> +			continue;
> +		break;
> +	}
> +
> +	fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
> +	pipe_config->pipe_bpp = reg_to_pixel_format(fmt);
> +
> +	bpp = mipi_dsi_pixel_format_to_bpp(pipe_config->pipe_bpp);
> +
> +	/* In terms of pixels */
> +	adjusted_mode->crtc_hdisplay =
> +				I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
> +	adjusted_mode->crtc_vdisplay =
> +				I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
> +	adjusted_mode->crtc_vtotal =
> +				I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
> +
> +	hactive = adjusted_mode->crtc_hdisplay;
> +	hfp = I915_READ(MIPI_HFP_COUNT(port));
> +
> +	/*
> +	 * meaningful for video mode non-burst sync pulse mode only,
> +	 * can be zero for non-burst sync events and burst modes
> +	 */
> +	hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
> +	hbp = I915_READ(MIPI_HBP_COUNT(port));
> +
> +	/* horizontal values are in terms of high speed byte clock */
> +	hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
> +					intel_dsi->burst_mode_ratio);
> +	hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
> +					intel_dsi->burst_mode_ratio);
> +	hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
> +					intel_dsi->burst_mode_ratio);
> +
> +	if (intel_dsi->dual_link) {
> +		hfp *= 2;
> +		hsync *= 2;
> +		hbp *= 2;
> +	}
> +
> +	/* vertical values are in terms of lines */
> +	vfp = I915_READ(MIPI_VFP_COUNT(port));
> +	vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
> +	vbp = I915_READ(MIPI_VBP_COUNT(port));
> +
> +	adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
> +	adjusted_mode->crtc_hsync_start =
> +				hfp + adjusted_mode->crtc_hdisplay;
> +	adjusted_mode->crtc_hsync_end =
> +				hsync + adjusted_mode->crtc_hsync_start;
> +	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
> +	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
> +
> +	adjusted_mode->crtc_vsync_start =
> +				vfp + adjusted_mode->crtc_vdisplay;
> +	adjusted_mode->crtc_vsync_end =
> +				vsync + adjusted_mode->crtc_vsync_start;
> +	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
> +	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
> +}
> +
> +
>   static void intel_dsi_get_config(struct intel_encoder *encoder,
>   				 struct intel_crtc_state *pipe_config)
>   {
> +	struct drm_device *dev = encoder->base.dev;
>   	u32 pclk;
>   	DRM_DEBUG_KMS("\n");
>   
>   	pipe_config->has_dsi_encoder = true;
>   
> +	if (IS_BROXTON(dev))
> +		bxt_dsi_get_pipe_config(encoder, pipe_config);
> +
>   	/*
>   	 * DPLL_MD is not used in case of DSI, reading will get some default value
>   	 * set dpll_md = 0

-- 
Thanks,
--Ram