[Intel-gfx] [PATCH v2] drm/i915/Gen9+: optional IPC enablement

[Dongwon Kim]

With IPC(Isochronous Priority Control) enabled,
display sends requests based on the priority of each
request. To enable it, a i915 param, i915.enable_ipc
should be set to 1.

v2: corrected matched type of enable_ipc in
    module_param_named_unsafe macro

Signed-off-by: Dongwon Kim <dongwon.kim at intel.com>
---
 drivers/gpu/drm/i915/i915_params.c | 5 +++++
 drivers/gpu/drm/i915/i915_params.h | 1 +
 drivers/gpu/drm/i915/i915_reg.h    | 1 +
 drivers/gpu/drm/i915/intel_pm.c    | 5 +++++
 4 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 1779f02..4d5ac80 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -58,6 +58,7 @@ struct i915_params i915 __read_mostly = {
 	.guc_log_level = -1,
 	.enable_dp_mst = true,
 	.inject_load_failure = 0,
+	.enable_ipc = 0,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);
@@ -210,3 +211,7 @@ MODULE_PARM_DESC(enable_dp_mst,
 module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400);
 MODULE_PARM_DESC(inject_load_failure,
 	"Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)");
+
+module_param_named_unsafe(enable_ipc, i915.enable_ipc, bool, 0400);
+MODULE_PARM_DESC(enable_ipc,
+	"Enable Isochronous Priority Control (1=enabled, 0=disabled [default]");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 02bc278..3b3fa1b 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -61,6 +61,7 @@ struct i915_params {
 	bool verbose_state_checks;
 	bool nuclear_pageflip;
 	bool enable_dp_mst;
+	bool enable_ipc;
 };
 
 extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 12f5103..0b638c5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5995,6 +5995,7 @@ enum skl_disp_power_wells {
 #define  DISP_FBC_WM_DIS		(1<<15)
 #define DISP_ARB_CTL2	_MMIO(0x45004)
 #define  DISP_DATA_PARTITION_5_6	(1<<6)
+#define  DISP_ENABLE_IPC		(1<<3)
 #define DBUF_CTL	_MMIO(0x45008)
 #define  DBUF_POWER_REQUEST		(1<<31)
 #define  DBUF_POWER_STATE		(1<<30)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9bc9c25..9c696c0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3682,6 +3682,11 @@ static void skl_update_wm(struct drm_crtc *crtc)
 	skl_write_wm_values(dev_priv, results);
 	skl_flush_wm_values(dev_priv, results);
 
+	/* optional IPC enablement */
+	if (i915.enable_ipc)
+		I915_WRITE(DISP_ARB_CTL2,
+			I915_READ(DISP_ARB_CTL2) | DISP_ENABLE_IPC);
+
 	/* store the new configuration */
 	dev_priv->wm.skl_hw = *results;
 }
-- 
1.9.1