[Intel-gfx] [PATCH] drm/i915/bxt: Set max cdclk frequency properly

[Imre Deak]

On ti, 2016-04-05 at 14:55 -0700, Matt Roper wrote:
> On Tue, Apr 05, 2016 at 02:37:19PM -0700, Matt Roper wrote:
> > intel_update_max_cdclk() doesn't have a switch case for Broxton, so
> > dev_priv->max_cdclk_freq gets set to whatever clock frequency we're
> > currently running at (e.g., 144 MHz) rather than the true
> > maximum.  This
> > causes our max dotclock to also be set too low and in turn leads
> > mode
> > verification to reject perfectly valid modes while loading EDID
> > firmware
> > blobs.
> > 
> > Cc: Imre Deak <imre.deak at intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> > ---
> 
> One thing I should have mentioned is that it's unclear to me whether we
> should be looking at the cdclk limit bits in the DFSM register like we
> do on SKL/KBL.  The bspec seems to indicate that the register in general
> applies to gen9, including BXT, but the actual meaning of the bits
> doesn't match up with the frequencies we have on BXT.

Yes, vendors could restrict the max CDCLK frequency via some method,
but we don't have that mechanism in place anyway and we would use the
hard-coded 624MHz if BIOS didn't enable CDCLK. So this is a correct
fix for now:

Reviewed-by: Imre Deak <imre.deak at intel.com>

> 
> 
> Matt
> 
> >  drivers/gpu/drm/i915/intel_display.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index af74cdb..924d851 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5261,6 +5261,8 @@ static void intel_update_max_cdclk(struct
> > drm_device *dev)
> >  			dev_priv->max_cdclk_freq = 450000;
> >  		else
> >  			dev_priv->max_cdclk_freq = 337500;
> > +	} else if (IS_BROXTON(dev)) {
> > +		dev_priv->max_cdclk_freq = 624000;
> >  	} else if (IS_BROADWELL(dev))  {
> >  		/*
> >  		 * FIXME with extra cooling we can allow
> > -- 
> > 2.1.4
> > 
>