[Intel-gfx] [PATCH] RFC drm/i915: Emulate 64bit registers for residency counters

[Ville Syrjälä]

On Thu, Apr 07, 2016 at 01:59:44PM +0100, Chris Wilson wrote:
> On Thu, Apr 07, 2016 at 03:49:01PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 07, 2016 at 01:37:35PM +0100, Chris Wilson wrote:
> > > On Thu, Apr 07, 2016 at 03:13:51PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 07, 2016 at 12:24:13PM +0100, Chris Wilson wrote:
> > > > > +static unsigned long calc_overflow_jiffies(struct drm_device *dev)
> > > > >  {
> > > > > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > > > > +	struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > +	u32 overflow_ms;
> > > > > +
> > > > > +	/* How many ticks per millisecond? */
> > > > > +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > > > +		overflow_ms = ~0u / dev_priv->czclk_freq;
> > > > 
> > > > Needs to account for the high range bit.
> > > 
> > > This was the bit I was uncertain about. Does the high range bit imply
> > > that is a 24-bit register? Or that the freq is measured differently?
> > 
> > The hardware apparently has a 40bit counter internally. In low range
> > mode the register exposes bits [31:0] of the counter, in high range
> > you get to see bits [39:8].
> 
> In that case the frequency would be reduced by >>8.
> 
> Can we set that bit ourselves? That puts the overflow into the 1 hour
> mark. Thanks,

I don't know if it's safe to frob the bit. I worry that something
outside our control might depend on it staying put.

-- 
Ville Syrjälä
Intel OTC