[Intel-gfx] [PATCH] drm/i915: Apply WaC6DisallowByGfxPause prior to SKL B0 / BXT A1

[yu.dai at intel.com]

From: Alex Dai <yu.dai at intel.com>

No need for this workaround since SKL C0 and BXT B0.

Issue: VIZ-7615
Signed-off-by: Alex Dai <yu.dai at intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index c0e5a01..ac85c28 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -327,15 +327,15 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 	/* Enable MIA caching. GuC clock gating is disabled. */
 	I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 
-	/* WaDisableMinuteIaClockGating:skl,bxt */
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+		/* WaDisableMinuteIaClockGating:skl,bxt */
 		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
 					      ~GUC_ENABLE_MIA_CLOCK_GATING));
-	}
 
-	/* WaC6DisallowByGfxPause*/
-	I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
+		/* WaC6DisallowByGfxPause*/
+		I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
+	}
 
 	if (IS_BROXTON(dev))
 		I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
-- 
2.5.0