[Intel-gfx] [PATCH 02/16] drm/i915/bxt: Fix GRC code register field definitions

[Imre Deak]

On pe, 2016-04-08 at 20:22 +0300, Ville Syrjälä wrote:
> On Fri, Apr 01, 2016 at 04:02:33PM +0300, Imre Deak wrote:
> > This has been corrected in BSpec quite some time ago, but we missed
> > it
> > somehow. The wrong field definitions resulted in configuring PHY0
> > with
> > an incorrect GRC value.
> > 
> > CC: Arthur J Runyan <arthur.j.runyan at intel.com>
> > Signed-off-by: Imre Deak <imre.deak at intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 6df3c59..f4a91bb 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1373,10 +1373,10 @@ enum skl_disp_power_wells {
> >   * FIXME: BSpec/CHV ConfigDB disagrees on the following two
> > fields, fix them
> >   * after testing.
> >   */
> 
> The FIXME can go, no?

Ah yea will remove it. So we did think about this already earlier..

> Matches my PHY docs as well as bspec now.
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> > -#define   GRC_CODE_SHIFT		23
> > -#define   GRC_CODE_MASK			(0x1FF <<
> > GRC_CODE_SHIFT)
> > +#define   GRC_CODE_SHIFT		24
> > +#define   GRC_CODE_MASK			(0xFF <<
> > GRC_CODE_SHIFT)
> >  #define   GRC_CODE_FAST_SHIFT		16
> > -#define   GRC_CODE_FAST_MASK		(0x7F <<
> > GRC_CODE_FAST_SHIFT)
> > +#define   GRC_CODE_FAST_MASK		(0xFF <<
> > GRC_CODE_FAST_SHIFT)
> >  #define   GRC_CODE_SLOW_SHIFT		8
> >  #define   GRC_CODE_SLOW_MASK		(0xFF <<
> > GRC_CODE_SLOW_SHIFT)
> >  #define   GRC_CODE_NOM_MASK		0xFF
> > -- 
> > 2.5.0
> > 
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>