[Intel-gfx] [PATCH 03/16] drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only

[Imre Deak]

On pe, 2016-04-08 at 21:02 +0300, Ville Syrjälä wrote:
> On Fri, Apr 01, 2016 at 04:02:34PM +0300, Imre Deak wrote:
> > This register is read-only, so we have never actually set
> > OCL2_LDOFUSE_PWR_DIS in it as specified by the specification. Add a
> > code
> > comment about this. I filed a specification update request to
> > clarify
> > this there.
> 
> Hmm. Interesting. It's r/w on my CHV, and the PHY spec agrees. Of
> course
> I can't really tell whether it has any effect on the x1 PHY. If I set
> it
> on the x2 PHY it definitely makes the channel unusable.

Note that meanwhile the corresponding BSpec change request got updated
to "Confirmed"/"Won't be fixed".

> > CC: Arthur J Runyan <arthur.j.runyan at intel.com>
> > Signed-off-by: Imre Deak <imre.deak at intel.com>
> > 
> > ---
> > 
> > [ Art, CC'ing you in case you know if this would have an effect on
> >   anything. ]
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 2758622..f91306e 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1798,6 +1798,9 @@ static void broxton_phy_init(struct
> > drm_i915_private *dev_priv,
> >  	 * enabled.
> >  	 * TODO: port C is only connected on BXT-P, so on BXT0/1
> > we should
> >  	 * power down the second channel on PHY0 as well.
> > +	 *
> > +	 * FIXME: Clarify programming of the following, the
> > register is
> > +	 * read-only with bit 6 fixed at 0 at least in stepping A.
> >  	 */
> >  	if (phy == DPIO_PHY1)
> >  		val |= OCL2_LDOFUSE_PWR_DIS;
> > -- 
> > 2.5.0
> > 
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>