[Intel-gfx] [PATCH 2/4] drm/i915: Fix serialisation of pipecontrol write vs semaphore signal

[Chris Wilson]

On Mon, Apr 11, 2016 at 11:34:54AM +0300, Ville Syrjälä wrote:
> On Sat, Apr 09, 2016 at 11:14:44AM +0100, Chris Wilson wrote:
> > In order for the MI_SEMAPHORE_SIGNAL command to wait until after the
> > pipecontrol writing the signal value is complete, we have to pause the
> > CS inside the PIPE_CONTROL with the CS_STALL bit.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 556924ee47f9..62d09cf2ea8f 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -1301,7 +1301,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
> >  		intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
> >  		intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
> >  					   PIPE_CONTROL_QW_WRITE |
> > -					   PIPE_CONTROL_FLUSH_ENABLE);
> > +					   PIPE_CONTROL_CS_STALL);
> 
> Doesn't this just stall when parsing the pipe control? Shouldn't
> we intead make sure the post-sync write is issued before the semaphore
> is signalled? (pipe_control /w post-sync write + second pipe control w/
> flush enable?)

No, afaik and can determine experimentally. The stall is after the
post-sync write. The pipe-control dosn't emit the write until it has
done the flush/invalidate and will not complete until the write is
commited (in theory, until it is coherent). The CS stall prevents the
command parser advancing until the pipecontrol is finished.

The syndrome when it is wrong is exactly like the missed interrupt one -
the waiter blocks forever as it is woken up before the sempahore value
is updated. Currently the code workarounds around this bug by the waiter
polling that value every N microseconds.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre