[Intel-gfx] [PATCH v4] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

[Chris Wilson]

On Tue, Apr 12, 2016 at 04:58:07PM +0300, Mika Kuoppala wrote:
> Michał Winiarski <michal.winiarski at intel.com> writes:
> 
> > [ text/plain ]
> > We started to use PIPE_CONTROL to write render ring seqno in order to
> > combat seqno write vs interrupt generation problems. This was introduced
> > by commit 7c17d377374d ("drm/i915: Use ordered seqno write interrupt
> > generation on gen8+ execlists").
> >
> > On gen8+ size of PIPE_CONTROL with Post Sync Operation should be
> > 6 dwords. When we're using older 5-dword variant it's possible to
> > observe inconsistent values written by PIPE_CONTROL with Post
> > Sync Operation from user batches, resulting in rendering corruptions.
> >
> > v2: Fix BAT failures
> > v3: Comments on alignment and thrashing high dword of seqno (Chris)
> > v4: Updated commit msg (Mika)
> >
> > Testcase: igt/gem_pipe_control_store_loop/*-qword-write
> > Issue: VIZ-7393
> > Cc: stable at vger.kernel.org
> > Cc: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala at intel.com>
> > Cc: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
> > Signed-off-by: Michał Winiarski <michal.winiarski at intel.com>
> 
> Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre