[Intel-gfx] [PATCH] drm/i915/dsi: fix CHV dsi encoder hardware state readout on port C

[Ville Syrjälä]

On Fri, Apr 15, 2016 at 03:47:31PM +0300, Jani Nikula wrote:
> Due to "some hardware limitation" the DPI enable bit in port C control
> register does not get set on VLV. As a workaround we check the status in
> pipe B conf register instead. The workaround was added in
> 
> commit c0beefd29fcb1ca998f0f9ba41be8539f8eeba9b
> Author: Gaurav K Singh <gaurav.k.singh at intel.com>
> Date:   Tue Dec 9 10:59:20 2014 +0530
> 
>     drm/i915: Software workaround for getting the HW status of DSI Port C on BYT
> 
> Empirical evidence (on Surface 3 with DSI on port C per VBT) shows that
> this is the case also on CHV, so extend the workaround to CHV. We still
> have the device ready register check in place, so this should not get
> confused with e.g. HDMI on pipe B.
> 
> This fixes a number of state checker warnings on CHV DSI port C.
> 
> Cc: stable at vger.kernel.org
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 9ff6435e7d38..f57adb0f0ee4 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -722,11 +722,12 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>  			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
>  		bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
>  
> -		/* Due to some hardware limitations on BYT, MIPI Port C DPI
> -		 * Enable bit does not get set. To check whether DSI Port C
> -		 * was enabled in BIOS, check the Pipe B enable bit
> +		/*
> +		 * Due to some hardware limitations on VLV/CHV, the DPI enable
> +		 * bit in port C control register does not get set. As a
> +		 * workaround, check pipe B conf instead.
>  		 */
> -		if (IS_VALLEYVIEW(dev) && port == PORT_C)
> +		if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && port == PORT_C)
>  			enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;

I saw your register dumps, so I believe it.

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

>  
>  		/* Try command mode if video mode not enabled */
> -- 
> 2.1.4

-- 
Ville Syrjälä
Intel OTC