[Intel-gfx] [PATCH 3/3] drm/i915: Always power on TX wells before CMN well on VLV

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Supposedly we need to power on the TX wells before CMN well on VLV.
We currently do that when enabling HDMI/DP ports, but when we enable
the CRT port we only power up the CMN well. So if someone enables the
CRT port first, and then HDMI/DP the wells will power up in the supposed
wrong order.

I can't actually reproduce any issues when I power on the wells in the
wrong order, so I'm not 100% convinced we couldn't just go back to the
original order. But I suppose it's possible there are machines that are
more sensitive, so let's make sure we follow the order we know to work.

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 259f66f94854..4fdd1ebdf6da 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1786,7 +1786,8 @@ static struct i915_power_well vlv_power_wells[] = {
 		.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
 			   VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
 			   VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
-			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS |
+			   VLV_DPIO_CMN_BC_POWER_DOMAINS,
 		.ops = &vlv_dpio_power_well_ops,
 		.data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
 	},
@@ -1795,7 +1796,8 @@ static struct i915_power_well vlv_power_wells[] = {
 		.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
 			   VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
 			   VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
-			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS |
+			   VLV_DPIO_CMN_BC_POWER_DOMAINS,
 		.ops = &vlv_dpio_power_well_ops,
 		.data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
 	},
@@ -1804,7 +1806,8 @@ static struct i915_power_well vlv_power_wells[] = {
 		.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
 			   VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
 			   VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
-			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS |
+			   VLV_DPIO_CMN_BC_POWER_DOMAINS,
 		.ops = &vlv_dpio_power_well_ops,
 		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
 	},
@@ -1813,7 +1816,8 @@ static struct i915_power_well vlv_power_wells[] = {
 		.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
 			   VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
 			   VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
-			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS |
+			   VLV_DPIO_CMN_BC_POWER_DOMAINS,
 		.ops = &vlv_dpio_power_well_ops,
 		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
 	},
-- 
2.7.4