[Intel-gfx] [PATCH v2 06/10] drm/i915: Undiplicate CHV encoders' post pll disable code

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:49PM +0300, Ander Conselvan de Oliveira wrote:
> The exact same code was used by HDMI and DP encoders, so move it to
> intel_dpio_phy.c.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>

There's a typo in the subject, but other than that:

Reviewed-by: Jim Bride <jim.bride at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_dp.c       | 30 +-----------------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 33 +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 30 +-----------------------------
>  4 files changed, 36 insertions(+), 58 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6f96c44..85c0610 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3563,6 +3563,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
>  void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
>  void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
>  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
> +void chv_phy_post_disable(struct intel_encoder *encoder);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 76a825c..cdacd8b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2868,35 +2868,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
>  
>  static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->sb_lock);
> -
> -	/* disable left/right clock distribution */
> -	if (pipe != PIPE_B) {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> -		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> -	} else {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> -		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> -	}
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> -
> -	/*
> -	 * Leave the power down bit cleared for at least one
> -	 * lane so that chv_powergate_phy_ch() will power
> -	 * on something when the channel is otherwise unused.
> -	 * When the port is off and the override is removed
> -	 * the lanes power down anyway, so otherwise it doesn't
> -	 * really matter what the state of power down bits is
> -	 * after this.
> -	 */
> -	chv_phy_powergate_lanes(encoder, false, 0x0);
> +	chv_phy_post_disable(encoder);
>  }
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index ad0e7be..2400554 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -336,3 +336,36 @@ void chv_phy_release_cl2_override(struct intel_encoder *encoder)
>  		dport->release_cl2_override = false;
>  	}
>  }
> +
> +void chv_phy_post_disable(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +
> +	/* disable left/right clock distribution */
> +	if (pipe != PIPE_B) {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> +		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> +	} else {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> +		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> +	}
> +
> +	mutex_unlock(&dev_priv->sb_lock);
> +
> +	/*
> +	 * Leave the power down bit cleared for at least one
> +	 * lane so that chv_powergate_phy_ch() will power
> +	 * on something when the channel is otherwise unused.
> +	 * When the port is off and the override is removed
> +	 * the lanes power down anyway, so otherwise it doesn't
> +	 * really matter what the state of power down bits is
> +	 * after this.
> +	 */
> +	chv_phy_powergate_lanes(encoder, false, 0x0);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index b4da7ee..f424af5 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1667,35 +1667,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  
>  static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->sb_lock);
> -
> -	/* disable left/right clock distribution */
> -	if (pipe != PIPE_B) {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> -		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> -	} else {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> -		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> -	}
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> -
> -	/*
> -	 * Leave the power down bit cleared for at least one
> -	 * lane so that chv_powergate_phy_ch() will power
> -	 * on something when the channel is otherwise unused.
> -	 * When the port is off and the override is removed
> -	 * the lanes power down anyway, so otherwise it doesn't
> -	 * really matter what the state of power down bits is
> -	 * after this.
> -	 */
> -	chv_phy_powergate_lanes(encoder, false, 0x0);
> +	chv_phy_post_disable(encoder);
>  }
>  
>  static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
> -- 
> 2.4.11
> 
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