[Intel-gfx] [PATCH 5/9] drm/i915: Enable i915 perf stream for Haswell OA unit

[Chris Wilson]

On Wed, Apr 20, 2016 at 03:23:10PM +0100, Robert Bragg wrote:
> +static void gen7_update_oacontrol_locked(struct drm_i915_private *dev_priv)
> +{
> +	assert_spin_locked(&dev_priv->perf.hook_lock);
> +
> +	if (dev_priv->perf.oa.exclusive_stream->enabled) {
> +		unsigned long ctx_id = 0;
> +
> +		if (dev_priv->perf.oa.exclusive_stream->ctx)
> +			ctx_id = dev_priv->perf.oa.specific_ctx_id;
> +
> +		if (dev_priv->perf.oa.exclusive_stream->ctx == NULL || ctx_id) {
> +			bool periodic = dev_priv->perf.oa.periodic;
> +			u32 period_exponent = dev_priv->perf.oa.period_exponent;
> +			u32 report_format = dev_priv->perf.oa.oa_buffer.format;
> +
> +			I915_WRITE(GEN7_OACONTROL,
> +				   (ctx_id & GEN7_OACONTROL_CTX_MASK) |
> +				   (period_exponent <<
> +				    GEN7_OACONTROL_TIMER_PERIOD_SHIFT) |
> +				   (periodic ?
> +				    GEN7_OACONTROL_TIMER_ENABLE : 0) |
> +				   (report_format <<
> +				    GEN7_OACONTROL_FORMAT_SHIFT) |
> +				   (ctx_id ?
> +				    GEN7_OACONTROL_PER_CTX_ENABLE : 0) |
> +				   GEN7_OACONTROL_ENABLE);

So this works by only recording when the OACONTROL context address
matches the CCID.

Rather than hooking into switch context and checking every batch whether
you have the exclusive context in case it changed address, you could
just pin the exclusive context when told by the user to bind perf to
that context. Then it will also have the same address until oa is
finished (and releases it vma pin).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre