[Intel-gfx] [PATCH 2/5] drm/i915: Parsing the PWM cntrl and CABC ON/OFF fields in VBT

[Jani Nikula]

On Wed, 30 Mar 2016, Jani Nikula <jani.nikula at intel.com> wrote:
> From: Deepak M <m.deepak at intel.com>
>
> For dual link panel scenarios there are new fields added in the
> VBT which indicate on which port the PWM cntrl and CABC ON/OFF
> commands needs to be sent.
>
> v2: Moving the comment to intel_dsi.h(Jani)
>
> v3: Renaming the field names (Jani)
>
> v4 by Jani: make this patch only about VBT
>
> Cc: Jani Nikula <jani.nikula at intel.com>
> Cc: Daniel Vetter <daniel.vetter at intel.com>
> Cc: Yetunde Adebisi <yetundex.adebisi at intel.com>
> Signed-off-by: Deepak M <m.deepak at intel.com>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>

Pushed to drm-intel-next-queued.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/intel_bios.c | 10 ++++++++++
>  drivers/gpu/drm/i915/intel_bios.h |  8 +++++++-
>  2 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 9c406b0f4173..6985519921b4 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -746,6 +746,16 @@ parse_mipi_config(struct drm_i915_private *dev_priv,
>  		return;
>  	}
>  
> +	/*
> +	 * These fields are introduced from the VBT version 197 onwards,
> +	 * so making sure that these bits are set zero in the previous
> +	 * versions.
> +	 */
> +	if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
> +		dev_priv->vbt.dsi.config->dl_dcs_cabc_ports = 0;
> +		dev_priv->vbt.dsi.config->dl_dcs_backlight_ports = 0;
> +	}
> +
>  	/* We have mandatory mipi config blocks. Initialize as generic panel */
>  	dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
> index ab0ea315eddb..149c3226e895 100644
> --- a/drivers/gpu/drm/i915/intel_bios.h
> +++ b/drivers/gpu/drm/i915/intel_bios.h
> @@ -113,7 +113,13 @@ struct mipi_config {
>  	u16 dual_link:2;
>  	u16 lane_cnt:2;
>  	u16 pixel_overlap:3;
> -	u16 rsvd3:9;
> +	u16 rgb_flip:1;
> +#define DL_DCS_PORT_A			0x00
> +#define DL_DCS_PORT_C			0x01
> +#define DL_DCS_PORT_A_AND_C		0x02
> +	u16 dl_dcs_cabc_ports:2;
> +	u16 dl_dcs_backlight_ports:2;
> +	u16 rsvd3:4;
>  
>  	u16 rsvd4;

-- 
Jani Nikula, Intel Open Source Technology Center