[Intel-gfx] [PATCH 6/9] drm/i915: Log watermark latencies on a single line per plane

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Compacts debug logging a bit so instead of:

 [drm:intel_print_wm_latency] Primary WM0 latency 20 (2.0 usec)
 [drm:intel_print_wm_latency] Primary WM1 latency 50 (25.0 usec)
 [drm:intel_print_wm_latency] Primary WM2 latency 90 (45.0 usec)
 [drm:intel_print_wm_latency] Primary WM3 latency 130 (65.0 usec)
 [drm:intel_print_wm_latency] Primary WM4 latency 160 (80.0 usec)
 [drm:intel_print_wm_latency] Sprite WM0 latency 20 (2.0 usec)
 [drm:intel_print_wm_latency] Sprite WM1 latency 50 (25.0 usec)
 [drm:intel_print_wm_latency] Sprite WM2 latency 90 (45.0 usec)
 [drm:intel_print_wm_latency] Sprite WM3 latency 130 (65.0 usec)
 [drm:intel_print_wm_latency] Sprite WM4 latency 160 (80.0 usec)
 [drm:intel_print_wm_latency] Cursor WM0 latency 20 (2.0 usec)
 [drm:intel_print_wm_latency] Cursor WM1 latency 50 (25.0 usec)
 [drm:intel_print_wm_latency] Cursor WM2 latency 90 (45.0 usec)
 [drm:intel_print_wm_latency] Cursor WM3 latency 130 (65.0 usec)
 [drm:intel_print_wm_latency] Cursor WM4 latency 160 (80.0 usec)

We get:

 [drm:intel_print_wm_latency] Primary plane latencies [2.0us (20), 25.0us (50), 45.0us (90), 65.0us (130), 80.0us (160)]
 [drm:intel_print_wm_latency] Sprite plane latencies [2.0us (20), 25.0us (50), 45.0us (90), 65.0us (130), 80.0us (160)]
 [drm:intel_print_wm_latency] Cursor plane latencies [2.0us (20), 25.0us (50), 45.0us (90), 65.0us (130), 80.0us (160)]

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 31 ++++++++++++++++++++++---------
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 695a464a5e64..23589eedf396 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2179,15 +2179,26 @@ static void intel_print_wm_latency(struct drm_device *dev,
 				   const uint16_t wm[8])
 {
 	int level, max_level = ilk_wm_max_level(dev);
+	bool error = false;
+	static const char *wm_msg = "%s plane latencies [";
 
 	for (level = 0; level <= max_level; level++) {
-		unsigned int latency = wm[level];
-
-		if (latency == 0) {
-			DRM_ERROR("%s WM%d latency not provided\n",
-				  name, level);
-			continue;
+		if (wm[level] == 0) {
+			error = true;
+			break;
 		}
+	}
+
+	if (error)
+		DRM_ERROR(wm_msg, name);
+	else
+		DRM_DEBUG_KMS(wm_msg, name);
+
+	if (!error && !(drm_debug && DRM_UT_KMS))
+		return;
+
+	for (level = 0; level <= max_level; level++) {
+		unsigned int latency = wm[level];
 
 		/*
 		 * - latencies are in us on gen9.
@@ -2198,10 +2209,12 @@ static void intel_print_wm_latency(struct drm_device *dev,
 		else if (level > 0)
 			latency *= 5;
 
-		DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
-			      name, level, wm[level],
-			      latency / 10, latency % 10);
+		if (level > 0)
+			printk(", ");
+		printk("%u.%uus (%u)", latency / 10, latency % 10, wm[level]);
 	}
+
+	printk("]\n");
 }
 
 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
-- 
1.9.1