[Intel-gfx] [PATCH 3/3] drm/i915: Fix comments about GMBUSFREQ register

[Ville Syrjälä]

On Wed, Apr 27, 2016 at 04:30:14PM +0300, Mika Kahola wrote:
> s/Programmng/Programming

It's straight from the spec, hence the [sic]

> 
> With this nitpick fixed, this is
> 
> Reviewed-by: Mika Kahola <mika.kahola at intel.com>
> 
> On Tue, 2016-04-26 at 19:46 +0300, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > The comment about GMBUSFREQ is confused. The spec actually explains
> > the 4MHz thing perfectly by noting that the 4MHz divider values is
> > actually just bits [9:2] not [9:0], hence the divide by 1000 correct.
> > Replace the confused note with a quote from the spec, and eliminate
> > the duplicated comment that snuck in.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 15 +++++----------
> >  1 file changed, 5 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index ea55dd331fac..ec9144ded255 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5311,18 +5311,13 @@ static void intel_update_cdclk(struct drm_device *dev)
> >  			 dev_priv->cdclk_freq);
> >  
> >  	/*
> > -	 * Program the gmbus_freq based on the cdclk frequency.
> > -	 * BSpec erroneously claims we should aim for 4MHz, but
> > -	 * in fact 1MHz is the correct frequency.
> > +	 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
> > +	 * Programmng [sic] note: bit[9:2] should be programmed to the number
> > +	 * of cdclk that generates 4MHz reference clock freq which is used to
> > +	 * generate GMBus clock. This will vary with the cdclk freq.
> >  	 */
> > -	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> > -		/*
> > -		 * Program the gmbus_freq based on the cdclk frequency.
> > -		 * BSpec erroneously claims we should aim for 4MHz, but
> > -		 * in fact 1MHz is the correct frequency.
> > -		 */
> > +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >  		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
> > -	}
> >  
> >  	if (dev_priv->max_cdclk_freq == 0)
> >  		intel_update_max_cdclk(dev);
> 
> -- 
> Mika Kahola - Intel OTC

-- 
Ville Syrjälä
Intel OTC